mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-26 06:33:19 -04:00
== Changes to existing drivers ==
- Rename child driver [axp288_battery => axp288_fuel_gauge]; axp20x
- Rename child driver [max77693-flash => max77693-led]; max77693
- Error handling fixes; intel_soc_pmic
- GPIO tweaking; intel_soc_pmic
- Remove non-DT code; vexpress-sysreg, tc3589x
- Remove unused/legacy code; ti_am335x_tscadc, rts5249, rtsx_gops, rtsx_pcr,
rtc-s5m, sec-core, max77693, menelaus,
wm5102-tables
- Trivial fixups; rtsx_pci, da9150-core, sec-core, max7769, max77693,
mc13xxx-core, dln2, hi6421-pmic-core, rk808, twl4030-power,
lpc_ich, menelaus, twl6040
- Update register/address values; rts5227, rts5249
- DT and/or binding document fixups; arizona, da9150, mt6397, axp20x,
qcom-rpm, qcom-spmi-pmic
- Couple of trivial core Kconfig fixups
- Remove use of seq_printf return value; ab8500-debugfs
- Remove __exit markups; menelaus, tps65010
- Fix platform-device name collisions; mfd-core
== New drivers/supported devices ==
- Add support for wm8280/wm8281 into arizona
- Add support for COMe-cBL6 into kempld-core
- Add support for rts524a and rts525a into rts5249
- Add support for ipq8064 into qcom_rpm
- Add support for extcon into axp20x
- New MediaTek MT6397 PMIC driver
- New Maxim MAX77843 PMIC dirver
- New Intel Quark X1000 I2C-GPIO driver
- New Skyworks SKY81452 driver
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVLQlhAAoJEFGvii+H/HdhnSYP/i7h+0/uvI32+49XlQWO/zZv
SIcnNcekSj/8MIIpSOZftY+ejdqyo8NHY0dvNTmxekY65ov/yXA6aJGDd5rr3xyL
hd9E5e5nwxc4UTV2kJwPBgCIKIjx/idRgOMTEpIa1v4KY8Gn43xc81X4s+BusbCE
WK8hPdBUePRDmMLrRzhkVHqrfeMSSLN5Z/fhmQehWqahE1asPZ2FOnTC6tFlGxgm
I55FAMvWey+qv4g28+nQrC9RQMetCL2f/6o53jMEQoaRQdJbbrxMybBnNvpcXwbR
JECPiV+2R0EqBd3xiT2gbPLAqmMDexIP1Cybh3BBRcFveJeJGqmMCFwMio6kotkA
IIMlYNcwczufPVWIIqz3U2OtJ5EWzxPgco2aA4a1Ej1nbUC29o829fMahZY0SR8m
O2zX/MpmYPZCg3mHOFQ4oPwalIM7oKv79NTV25Ks9r+rv+zNaBc8TPCE/Oxkxfj8
IdJ/vKQaKMmMZA1THO8HMK9qAQV7vZL12XquVzrAgq40RZa+nOUXEk0J0rHI0VaO
BHNMBv1D3iNQfR7cWAappDavhoZcFtIY/Z9x7OsLYm/W8+CxhdAafMNH0AJPlfts
NR7RoNtStumXdq6QzDdA27Mp1sXkHz/kgGMVE4t9mdLVmD9C0MqVi8VPFUN+sST0
vAKAhQ/cnXCKVxe6I9/3
=QPNn
-----END PGP SIGNATURE-----
Merge tag 'mfd-for-linus-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones:
"Changes to existing drivers:
- Rename child driver [axp288_battery => axp288_fuel_gauge]; axp20x
- Rename child driver [max77693-flash => max77693-led]; max77693
- Error handling fixes; intel_soc_pmic
- GPIO tweaking; intel_soc_pmic
- Remove non-DT code; vexpress-sysreg, tc3589x
- Remove unused/legacy code; ti_am335x_tscadc, rts5249, rtsx_gops, rtsx_pcr,
rtc-s5m, sec-core, max77693, menelaus,
wm5102-tables
- Trivial fixups; rtsx_pci, da9150-core, sec-core, max7769, max77693,
mc13xxx-core, dln2, hi6421-pmic-core, rk808, twl4030-power,
lpc_ich, menelaus, twl6040
- Update register/address values; rts5227, rts5249
- DT and/or binding document fixups; arizona, da9150, mt6397, axp20x,
qcom-rpm, qcom-spmi-pmic
- Couple of trivial core Kconfig fixups
- Remove use of seq_printf return value; ab8500-debugfs
- Remove __exit markups; menelaus, tps65010
- Fix platform-device name collisions; mfd-core
New drivers/supported devices:
- Add support for wm8280/wm8281 into arizona
- Add support for COMe-cBL6 into kempld-core
- Add support for rts524a and rts525a into rts5249
- Add support for ipq8064 into qcom_rpm
- Add support for extcon into axp20x
- New MediaTek MT6397 PMIC driver
- New Maxim MAX77843 PMIC dirver
- New Intel Quark X1000 I2C-GPIO driver
- New Skyworks SKY81452 driver"
* tag 'mfd-for-linus-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (76 commits)
mfd: sec: Fix RTC alarm interrupt number on S2MPS11
mfd: wm5102: Remove registers for output 3R from readable list
mfd: tps65010: Remove incorrect __exit markups
mfd: devicetree: bindings: Add Qualcomm RPM regulator subnodes
mfd: axp20x: Add support for extcon cell
mfd: lpc_ich: Sort IDs
mfd: twl6040: Remove wrong and unneeded "platform:twl6040" modalias
mfd: qcom-spmi-pmic: Add specific compatible strings for Qualcomm's SPMI PMIC's
mfd: axp20x: Fix duplicate const for model names
mfd: menelaus: Use macro for magic number
mfd: menelaus: Drop support for SW controller VCORE
mfd: menelaus: Delete omap_has_menelaus
mfd: arizona: Correct type of gpio_defaults
mfd: lpc_ich: Sort IDs
mfd: Fix a typo in Kconfig
mfd: qcom_rpm: Add support for IPQ8064
mfd: devicetree: qcom_rpm: Document IPQ8064 resources
mfd: core: Fix platform-device name collisions
mfd: intel_quark_i2c_gpio: Don't crash if !DMI
dt-bindings: Add vendor-prefix for X-Powers
...
This commit is contained in:
Linus Torvalds
commit
f0c1bc95a1
82 changed files with 4256 additions and 1185 deletions
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@ -24,6 +24,7 @@ enum arizona_type {
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WM5102 = 1,
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WM5110 = 2,
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WM8997 = 3,
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WM8280 = 4,
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};
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#define ARIZONA_IRQ_GP1 0
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@ -1,96 +0,0 @@
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/*
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* GPIO configuration for Arizona devices
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*
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* Copyright 2013 Wolfson Microelectronics. PLC.
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*
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* Author: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ARIZONA_GPIO_H
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#define _ARIZONA_GPIO_H
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#define ARIZONA_GP_FN_TXLRCLK 0x00
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#define ARIZONA_GP_FN_GPIO 0x01
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#define ARIZONA_GP_FN_IRQ1 0x02
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#define ARIZONA_GP_FN_IRQ2 0x03
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#define ARIZONA_GP_FN_OPCLK 0x04
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#define ARIZONA_GP_FN_FLL1_OUT 0x05
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#define ARIZONA_GP_FN_FLL2_OUT 0x06
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#define ARIZONA_GP_FN_PWM1 0x08
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#define ARIZONA_GP_FN_PWM2 0x09
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#define ARIZONA_GP_FN_SYSCLK_UNDERCLOCKED 0x0A
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#define ARIZONA_GP_FN_ASYNCCLK_UNDERCLOCKED 0x0B
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#define ARIZONA_GP_FN_FLL1_LOCK 0x0C
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#define ARIZONA_GP_FN_FLL2_LOCK 0x0D
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#define ARIZONA_GP_FN_FLL1_CLOCK_OK 0x0F
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#define ARIZONA_GP_FN_FLL2_CLOCK_OK 0x10
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#define ARIZONA_GP_FN_HEADPHONE_DET 0x12
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#define ARIZONA_GP_FN_MIC_DET 0x13
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#define ARIZONA_GP_FN_WSEQ_STATUS 0x15
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#define ARIZONA_GP_FN_CIF_ADDRESS_ERROR 0x16
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#define ARIZONA_GP_FN_ASRC1_LOCK 0x1A
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#define ARIZONA_GP_FN_ASRC2_LOCK 0x1B
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#define ARIZONA_GP_FN_ASRC_CONFIG_ERROR 0x1C
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#define ARIZONA_GP_FN_DRC1_SIGNAL_DETECT 0x1D
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#define ARIZONA_GP_FN_DRC1_ANTICLIP 0x1E
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#define ARIZONA_GP_FN_DRC1_DECAY 0x1F
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#define ARIZONA_GP_FN_DRC1_NOISE 0x20
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#define ARIZONA_GP_FN_DRC1_QUICK_RELEASE 0x21
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#define ARIZONA_GP_FN_DRC2_SIGNAL_DETECT 0x22
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#define ARIZONA_GP_FN_DRC2_ANTICLIP 0x23
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#define ARIZONA_GP_FN_DRC2_DECAY 0x24
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#define ARIZONA_GP_FN_DRC2_NOISE 0x25
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#define ARIZONA_GP_FN_DRC2_QUICK_RELEASE 0x26
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#define ARIZONA_GP_FN_MIXER_DROPPED_SAMPLE 0x27
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#define ARIZONA_GP_FN_AIF1_CONFIG_ERROR 0x28
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#define ARIZONA_GP_FN_AIF2_CONFIG_ERROR 0x29
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#define ARIZONA_GP_FN_AIF3_CONFIG_ERROR 0x2A
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#define ARIZONA_GP_FN_SPK_TEMP_SHUTDOWN 0x2B
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#define ARIZONA_GP_FN_SPK_TEMP_WARNING 0x2C
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#define ARIZONA_GP_FN_UNDERCLOCKED 0x2D
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#define ARIZONA_GP_FN_OVERCLOCKED 0x2E
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#define ARIZONA_GP_FN_DSP_IRQ1 0x35
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#define ARIZONA_GP_FN_DSP_IRQ2 0x36
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#define ARIZONA_GP_FN_ASYNC_OPCLK 0x3D
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#define ARIZONA_GP_FN_BOOT_DONE 0x44
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#define ARIZONA_GP_FN_DSP1_RAM_READY 0x45
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#define ARIZONA_GP_FN_SYSCLK_ENA_STATUS 0x4B
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#define ARIZONA_GP_FN_ASYNCCLK_ENA_STATUS 0x4C
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#define ARIZONA_GPN_DIR 0x8000 /* GPN_DIR */
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#define ARIZONA_GPN_DIR_MASK 0x8000 /* GPN_DIR */
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#define ARIZONA_GPN_DIR_SHIFT 15 /* GPN_DIR */
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#define ARIZONA_GPN_DIR_WIDTH 1 /* GPN_DIR */
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#define ARIZONA_GPN_PU 0x4000 /* GPN_PU */
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#define ARIZONA_GPN_PU_MASK 0x4000 /* GPN_PU */
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#define ARIZONA_GPN_PU_SHIFT 14 /* GPN_PU */
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#define ARIZONA_GPN_PU_WIDTH 1 /* GPN_PU */
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#define ARIZONA_GPN_PD 0x2000 /* GPN_PD */
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#define ARIZONA_GPN_PD_MASK 0x2000 /* GPN_PD */
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#define ARIZONA_GPN_PD_SHIFT 13 /* GPN_PD */
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#define ARIZONA_GPN_PD_WIDTH 1 /* GPN_PD */
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#define ARIZONA_GPN_LVL 0x0800 /* GPN_LVL */
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#define ARIZONA_GPN_LVL_MASK 0x0800 /* GPN_LVL */
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#define ARIZONA_GPN_LVL_SHIFT 11 /* GPN_LVL */
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#define ARIZONA_GPN_LVL_WIDTH 1 /* GPN_LVL */
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#define ARIZONA_GPN_POL 0x0400 /* GPN_POL */
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#define ARIZONA_GPN_POL_MASK 0x0400 /* GPN_POL */
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#define ARIZONA_GPN_POL_SHIFT 10 /* GPN_POL */
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#define ARIZONA_GPN_POL_WIDTH 1 /* GPN_POL */
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#define ARIZONA_GPN_OP_CFG 0x0200 /* GPN_OP_CFG */
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#define ARIZONA_GPN_OP_CFG_MASK 0x0200 /* GPN_OP_CFG */
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#define ARIZONA_GPN_OP_CFG_SHIFT 9 /* GPN_OP_CFG */
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#define ARIZONA_GPN_OP_CFG_WIDTH 1 /* GPN_OP_CFG */
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#define ARIZONA_GPN_DB 0x0100 /* GPN_DB */
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#define ARIZONA_GPN_DB_MASK 0x0100 /* GPN_DB */
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#define ARIZONA_GPN_DB_SHIFT 8 /* GPN_DB */
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#define ARIZONA_GPN_DB_WIDTH 1 /* GPN_DB */
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#define ARIZONA_GPN_FN_MASK 0x007F /* GPN_DB */
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#define ARIZONA_GPN_FN_SHIFT 0 /* GPN_DB */
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#define ARIZONA_GPN_FN_WIDTH 7 /* GPN_DB */
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#endif
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@ -11,31 +11,26 @@
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#ifndef _ARIZONA_PDATA_H
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#define _ARIZONA_PDATA_H
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#define ARIZONA_GPN_DIR 0x8000 /* GPN_DIR */
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#include <dt-bindings/mfd/arizona.h>
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#define ARIZONA_GPN_DIR_MASK 0x8000 /* GPN_DIR */
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#define ARIZONA_GPN_DIR_SHIFT 15 /* GPN_DIR */
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#define ARIZONA_GPN_DIR_WIDTH 1 /* GPN_DIR */
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#define ARIZONA_GPN_PU 0x4000 /* GPN_PU */
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#define ARIZONA_GPN_PU_MASK 0x4000 /* GPN_PU */
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#define ARIZONA_GPN_PU_SHIFT 14 /* GPN_PU */
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#define ARIZONA_GPN_PU_WIDTH 1 /* GPN_PU */
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#define ARIZONA_GPN_PD 0x2000 /* GPN_PD */
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#define ARIZONA_GPN_PD_MASK 0x2000 /* GPN_PD */
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#define ARIZONA_GPN_PD_SHIFT 13 /* GPN_PD */
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#define ARIZONA_GPN_PD_WIDTH 1 /* GPN_PD */
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#define ARIZONA_GPN_LVL 0x0800 /* GPN_LVL */
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#define ARIZONA_GPN_LVL_MASK 0x0800 /* GPN_LVL */
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#define ARIZONA_GPN_LVL_SHIFT 11 /* GPN_LVL */
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#define ARIZONA_GPN_LVL_WIDTH 1 /* GPN_LVL */
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#define ARIZONA_GPN_POL 0x0400 /* GPN_POL */
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#define ARIZONA_GPN_POL_MASK 0x0400 /* GPN_POL */
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#define ARIZONA_GPN_POL_SHIFT 10 /* GPN_POL */
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#define ARIZONA_GPN_POL_WIDTH 1 /* GPN_POL */
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#define ARIZONA_GPN_OP_CFG 0x0200 /* GPN_OP_CFG */
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#define ARIZONA_GPN_OP_CFG_MASK 0x0200 /* GPN_OP_CFG */
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#define ARIZONA_GPN_OP_CFG_SHIFT 9 /* GPN_OP_CFG */
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#define ARIZONA_GPN_OP_CFG_WIDTH 1 /* GPN_OP_CFG */
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#define ARIZONA_GPN_DB 0x0100 /* GPN_DB */
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#define ARIZONA_GPN_DB_MASK 0x0100 /* GPN_DB */
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#define ARIZONA_GPN_DB_SHIFT 8 /* GPN_DB */
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#define ARIZONA_GPN_DB_WIDTH 1 /* GPN_DB */
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@ -45,23 +40,10 @@
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#define ARIZONA_MAX_GPIO 5
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#define ARIZONA_32KZ_MCLK1 1
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#define ARIZONA_32KZ_MCLK2 2
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#define ARIZONA_32KZ_NONE 3
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#define ARIZONA_MAX_INPUT 4
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#define ARIZONA_DMIC_MICVDD 0
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#define ARIZONA_DMIC_MICBIAS1 1
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#define ARIZONA_DMIC_MICBIAS2 2
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#define ARIZONA_DMIC_MICBIAS3 3
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#define ARIZONA_MAX_MICBIAS 3
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#define ARIZONA_INMODE_DIFF 0
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#define ARIZONA_INMODE_SE 1
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#define ARIZONA_INMODE_DMIC 2
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#define ARIZONA_MAX_OUTPUT 6
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#define ARIZONA_MAX_AIF 3
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@ -112,7 +94,7 @@ struct arizona_pdata {
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int gpio_base;
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/** Pin state for GPIO pins */
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int gpio_defaults[ARIZONA_MAX_GPIO];
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unsigned int gpio_defaults[ARIZONA_MAX_GPIO];
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/**
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* Maximum number of channels clocks will be generated for,
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|
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|
|
@ -87,6 +87,7 @@ enum max77693_pmic_reg {
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/* MAX77693 ITORCH register */
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#define TORCH_IOUT1_SHIFT 0
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#define TORCH_IOUT2_SHIFT 4
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#define TORCH_IOUT_MASK(x) (0xf << (x))
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#define TORCH_IOUT_MIN 15625
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#define TORCH_IOUT_MAX 250000
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#define TORCH_IOUT_STEP 15625
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@ -113,8 +114,8 @@ enum max77693_pmic_reg {
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#define FLASH_EN_FLASH 0x1
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#define FLASH_EN_TORCH 0x2
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#define FLASH_EN_ON 0x3
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#define FLASH_EN_SHIFT(x) (6 - ((x) - 1) * 2)
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#define TORCH_EN_SHIFT(x) (2 - ((x) - 1) * 2)
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#define FLASH_EN_SHIFT(x) (6 - (x) * 2)
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#define TORCH_EN_SHIFT(x) (2 - (x) * 2)
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/* MAX77693 MAX_FLASH1 register */
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#define MAX_FLASH1_MAX_FL_EN 0x80
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|
|
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|
@ -81,19 +81,6 @@ enum max77693_led_boost_mode {
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MAX77693_LED_BOOST_FIXED,
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};
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struct max77693_led_platform_data {
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u32 fleds[2];
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u32 iout_torch[2];
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u32 iout_flash[2];
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u32 trigger[2];
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u32 trigger_type[2];
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u32 num_leds;
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u32 boost_mode;
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u32 flash_timeout;
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u32 boost_vout;
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u32 low_vsys;
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};
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/* MAX77693 */
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struct max77693_platform_data {
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|
|
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|||
454
include/linux/mfd/max77843-private.h
Normal file
454
include/linux/mfd/max77843-private.h
Normal file
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|
@ -0,0 +1,454 @@
|
|||
/*
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||||
* Common variables for the Maxim MAX77843 driver
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||||
*
|
||||
* Copyright (C) 2015 Samsung Electronics
|
||||
* Author: Jaewon Kim <jaewon02.kim@samsung.com>
|
||||
* Author: Beomho Seo <beomho.seo@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __MAX77843_PRIVATE_H_
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#define __MAX77843_PRIVATE_H_
|
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|
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#include <linux/i2c.h>
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#include <linux/regmap.h>
|
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|
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#define I2C_ADDR_TOPSYS (0xCC >> 1)
|
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#define I2C_ADDR_CHG (0xD2 >> 1)
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#define I2C_ADDR_FG (0x6C >> 1)
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#define I2C_ADDR_MUIC (0x4A >> 1)
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|
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/* Topsys, Haptic and LED registers */
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enum max77843_sys_reg {
|
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MAX77843_SYS_REG_PMICID = 0x00,
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MAX77843_SYS_REG_PMICREV = 0x01,
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MAX77843_SYS_REG_MAINCTRL1 = 0x02,
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MAX77843_SYS_REG_INTSRC = 0x22,
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MAX77843_SYS_REG_INTSRCMASK = 0x23,
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MAX77843_SYS_REG_SYSINTSRC = 0x24,
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MAX77843_SYS_REG_SYSINTMASK = 0x26,
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MAX77843_SYS_REG_TOPSYS_STAT = 0x28,
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MAX77843_SYS_REG_SAFEOUTCTRL = 0xC6,
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MAX77843_SYS_REG_END,
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};
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enum max77843_haptic_reg {
|
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MAX77843_HAP_REG_MCONFIG = 0x10,
|
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|
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MAX77843_HAP_REG_END,
|
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};
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|
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enum max77843_led_reg {
|
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MAX77843_LED_REG_LEDEN = 0x30,
|
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MAX77843_LED_REG_LED0BRT = 0x31,
|
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MAX77843_LED_REG_LED1BRT = 0x32,
|
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MAX77843_LED_REG_LED2BRT = 0x33,
|
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MAX77843_LED_REG_LED3BRT = 0x34,
|
||||
MAX77843_LED_REG_LEDBLNK = 0x38,
|
||||
MAX77843_LED_REG_LEDRAMP = 0x36,
|
||||
|
||||
MAX77843_LED_REG_END,
|
||||
};
|
||||
|
||||
/* Charger registers */
|
||||
enum max77843_charger_reg {
|
||||
MAX77843_CHG_REG_CHG_INT = 0xB0,
|
||||
MAX77843_CHG_REG_CHG_INT_MASK = 0xB1,
|
||||
MAX77843_CHG_REG_CHG_INT_OK = 0xB2,
|
||||
MAX77843_CHG_REG_CHG_DTLS_00 = 0xB3,
|
||||
MAX77843_CHG_REG_CHG_DTLS_01 = 0xB4,
|
||||
MAX77843_CHG_REG_CHG_DTLS_02 = 0xB5,
|
||||
MAX77843_CHG_REG_CHG_CNFG_00 = 0xB7,
|
||||
MAX77843_CHG_REG_CHG_CNFG_01 = 0xB8,
|
||||
MAX77843_CHG_REG_CHG_CNFG_02 = 0xB9,
|
||||
MAX77843_CHG_REG_CHG_CNFG_03 = 0xBA,
|
||||
MAX77843_CHG_REG_CHG_CNFG_04 = 0xBB,
|
||||
MAX77843_CHG_REG_CHG_CNFG_06 = 0xBD,
|
||||
MAX77843_CHG_REG_CHG_CNFG_07 = 0xBE,
|
||||
MAX77843_CHG_REG_CHG_CNFG_09 = 0xC0,
|
||||
MAX77843_CHG_REG_CHG_CNFG_10 = 0xC1,
|
||||
MAX77843_CHG_REG_CHG_CNFG_11 = 0xC2,
|
||||
MAX77843_CHG_REG_CHG_CNFG_12 = 0xC3,
|
||||
|
||||
MAX77843_CHG_REG_END,
|
||||
};
|
||||
|
||||
/* Fuel gauge registers */
|
||||
enum max77843_fuelgauge {
|
||||
MAX77843_FG_REG_STATUS = 0x00,
|
||||
MAX77843_FG_REG_VALRT_TH = 0x01,
|
||||
MAX77843_FG_REG_TALRT_TH = 0x02,
|
||||
MAX77843_FG_REG_SALRT_TH = 0x03,
|
||||
MAX77843_FG_RATE_AT_RATE = 0x04,
|
||||
MAX77843_FG_REG_REMCAP_REP = 0x05,
|
||||
MAX77843_FG_REG_SOCREP = 0x06,
|
||||
MAX77843_FG_REG_AGE = 0x07,
|
||||
MAX77843_FG_REG_TEMP = 0x08,
|
||||
MAX77843_FG_REG_VCELL = 0x09,
|
||||
MAX77843_FG_REG_CURRENT = 0x0A,
|
||||
MAX77843_FG_REG_AVG_CURRENT = 0x0B,
|
||||
MAX77843_FG_REG_SOCMIX = 0x0D,
|
||||
MAX77843_FG_REG_SOCAV = 0x0E,
|
||||
MAX77843_FG_REG_REMCAP_MIX = 0x0F,
|
||||
MAX77843_FG_REG_FULLCAP = 0x10,
|
||||
MAX77843_FG_REG_AVG_TEMP = 0x16,
|
||||
MAX77843_FG_REG_CYCLES = 0x17,
|
||||
MAX77843_FG_REG_AVG_VCELL = 0x19,
|
||||
MAX77843_FG_REG_CONFIG = 0x1D,
|
||||
MAX77843_FG_REG_REMCAP_AV = 0x1F,
|
||||
MAX77843_FG_REG_FULLCAP_NOM = 0x23,
|
||||
MAX77843_FG_REG_MISCCFG = 0x2B,
|
||||
MAX77843_FG_REG_RCOMP = 0x38,
|
||||
MAX77843_FG_REG_FSTAT = 0x3D,
|
||||
MAX77843_FG_REG_DQACC = 0x45,
|
||||
MAX77843_FG_REG_DPACC = 0x46,
|
||||
MAX77843_FG_REG_OCV = 0xEE,
|
||||
MAX77843_FG_REG_VFOCV = 0xFB,
|
||||
MAX77843_FG_SOCVF = 0xFF,
|
||||
|
||||
MAX77843_FG_END,
|
||||
};
|
||||
|
||||
/* MUIC registers */
|
||||
enum max77843_muic_reg {
|
||||
MAX77843_MUIC_REG_ID = 0x00,
|
||||
MAX77843_MUIC_REG_INT1 = 0x01,
|
||||
MAX77843_MUIC_REG_INT2 = 0x02,
|
||||
MAX77843_MUIC_REG_INT3 = 0x03,
|
||||
MAX77843_MUIC_REG_STATUS1 = 0x04,
|
||||
MAX77843_MUIC_REG_STATUS2 = 0x05,
|
||||
MAX77843_MUIC_REG_STATUS3 = 0x06,
|
||||
MAX77843_MUIC_REG_INTMASK1 = 0x07,
|
||||
MAX77843_MUIC_REG_INTMASK2 = 0x08,
|
||||
MAX77843_MUIC_REG_INTMASK3 = 0x09,
|
||||
MAX77843_MUIC_REG_CDETCTRL1 = 0x0A,
|
||||
MAX77843_MUIC_REG_CDETCTRL2 = 0x0B,
|
||||
MAX77843_MUIC_REG_CONTROL1 = 0x0C,
|
||||
MAX77843_MUIC_REG_CONTROL2 = 0x0D,
|
||||
MAX77843_MUIC_REG_CONTROL3 = 0x0E,
|
||||
MAX77843_MUIC_REG_CONTROL4 = 0x16,
|
||||
MAX77843_MUIC_REG_HVCONTROL1 = 0x17,
|
||||
MAX77843_MUIC_REG_HVCONTROL2 = 0x18,
|
||||
|
||||
MAX77843_MUIC_REG_END,
|
||||
};
|
||||
|
||||
enum max77843_irq {
|
||||
/* Topsys: SYSTEM */
|
||||
MAX77843_SYS_IRQ_SYSINTSRC_SYSUVLO_INT,
|
||||
MAX77843_SYS_IRQ_SYSINTSRC_SYSOVLO_INT,
|
||||
MAX77843_SYS_IRQ_SYSINTSRC_TSHDN_INT,
|
||||
MAX77843_SYS_IRQ_SYSINTSRC_TM_INT,
|
||||
|
||||
/* Charger: CHG_INT */
|
||||
MAX77843_CHG_IRQ_CHG_INT_BYP_I,
|
||||
MAX77843_CHG_IRQ_CHG_INT_BATP_I,
|
||||
MAX77843_CHG_IRQ_CHG_INT_BAT_I,
|
||||
MAX77843_CHG_IRQ_CHG_INT_CHG_I,
|
||||
MAX77843_CHG_IRQ_CHG_INT_WCIN_I,
|
||||
MAX77843_CHG_IRQ_CHG_INT_CHGIN_I,
|
||||
MAX77843_CHG_IRQ_CHG_INT_AICL_I,
|
||||
|
||||
MAX77843_IRQ_NUM,
|
||||
};
|
||||
|
||||
enum max77843_irq_muic {
|
||||
/* MUIC: INT1 */
|
||||
MAX77843_MUIC_IRQ_INT1_ADC,
|
||||
MAX77843_MUIC_IRQ_INT1_ADCERROR,
|
||||
MAX77843_MUIC_IRQ_INT1_ADC1K,
|
||||
|
||||
/* MUIC: INT2 */
|
||||
MAX77843_MUIC_IRQ_INT2_CHGTYP,
|
||||
MAX77843_MUIC_IRQ_INT2_CHGDETRUN,
|
||||
MAX77843_MUIC_IRQ_INT2_DCDTMR,
|
||||
MAX77843_MUIC_IRQ_INT2_DXOVP,
|
||||
MAX77843_MUIC_IRQ_INT2_VBVOLT,
|
||||
|
||||
/* MUIC: INT3 */
|
||||
MAX77843_MUIC_IRQ_INT3_VBADC,
|
||||
MAX77843_MUIC_IRQ_INT3_VDNMON,
|
||||
MAX77843_MUIC_IRQ_INT3_DNRES,
|
||||
MAX77843_MUIC_IRQ_INT3_MPNACK,
|
||||
MAX77843_MUIC_IRQ_INT3_MRXBUFOW,
|
||||
MAX77843_MUIC_IRQ_INT3_MRXTRF,
|
||||
MAX77843_MUIC_IRQ_INT3_MRXPERR,
|
||||
MAX77843_MUIC_IRQ_INT3_MRXRDY,
|
||||
|
||||
MAX77843_MUIC_IRQ_NUM,
|
||||
};
|
||||
|
||||
/* MAX77843 interrupts */
|
||||
#define MAX77843_SYS_IRQ_SYSUVLO_INT BIT(0)
|
||||
#define MAX77843_SYS_IRQ_SYSOVLO_INT BIT(1)
|
||||
#define MAX77843_SYS_IRQ_TSHDN_INT BIT(2)
|
||||
#define MAX77843_SYS_IRQ_TM_INT BIT(3)
|
||||
|
||||
/* MAX77843 MAINCTRL1 register */
|
||||
#define MAINCTRL1_BIASEN_SHIFT 7
|
||||
#define MAX77843_MAINCTRL1_BIASEN_MASK BIT(MAINCTRL1_BIASEN_SHIFT)
|
||||
|
||||
/* MAX77843 MCONFIG register */
|
||||
#define MCONFIG_MODE_SHIFT 7
|
||||
#define MCONFIG_MEN_SHIFT 6
|
||||
#define MCONFIG_PDIV_SHIFT 0
|
||||
|
||||
#define MAX77843_MCONFIG_MODE_MASK BIT(MCONFIG_MODE_SHIFT)
|
||||
#define MAX77843_MCONFIG_MEN_MASK BIT(MCONFIG_MEN_SHIFT)
|
||||
#define MAX77843_MCONFIG_PDIV_MASK (0x3 << MCONFIG_PDIV_SHIFT)
|
||||
|
||||
/* Max77843 charger insterrupts */
|
||||
#define MAX77843_CHG_BYP_I BIT(0)
|
||||
#define MAX77843_CHG_BATP_I BIT(2)
|
||||
#define MAX77843_CHG_BAT_I BIT(3)
|
||||
#define MAX77843_CHG_CHG_I BIT(4)
|
||||
#define MAX77843_CHG_WCIN_I BIT(5)
|
||||
#define MAX77843_CHG_CHGIN_I BIT(6)
|
||||
#define MAX77843_CHG_AICL_I BIT(7)
|
||||
|
||||
/* MAX77843 CHG_INT_OK register */
|
||||
#define MAX77843_CHG_BYP_OK BIT(0)
|
||||
#define MAX77843_CHG_BATP_OK BIT(2)
|
||||
#define MAX77843_CHG_BAT_OK BIT(3)
|
||||
#define MAX77843_CHG_CHG_OK BIT(4)
|
||||
#define MAX77843_CHG_WCIN_OK BIT(5)
|
||||
#define MAX77843_CHG_CHGIN_OK BIT(6)
|
||||
#define MAX77843_CHG_AICL_OK BIT(7)
|
||||
|
||||
/* MAX77843 CHG_DETAILS_00 register */
|
||||
#define MAX77843_CHG_BAT_DTLS BIT(0)
|
||||
|
||||
/* MAX77843 CHG_DETAILS_01 register */
|
||||
#define MAX77843_CHG_DTLS_MASK 0x0f
|
||||
#define MAX77843_CHG_PQ_MODE 0x00
|
||||
#define MAX77843_CHG_CC_MODE 0x01
|
||||
#define MAX77843_CHG_CV_MODE 0x02
|
||||
#define MAX77843_CHG_TO_MODE 0x03
|
||||
#define MAX77843_CHG_DO_MODE 0x04
|
||||
#define MAX77843_CHG_HT_MODE 0x05
|
||||
#define MAX77843_CHG_TF_MODE 0x06
|
||||
#define MAX77843_CHG_TS_MODE 0x07
|
||||
#define MAX77843_CHG_OFF_MODE 0x08
|
||||
|
||||
#define MAX77843_CHG_BAT_DTLS_MASK 0xf0
|
||||
#define MAX77843_CHG_NO_BAT (0x00 << 4)
|
||||
#define MAX77843_CHG_LOW_VOLT_BAT (0x01 << 4)
|
||||
#define MAX77843_CHG_LONG_BAT_TIME (0x02 << 4)
|
||||
#define MAX77843_CHG_OK_BAT (0x03 << 4)
|
||||
#define MAX77843_CHG_OK_LOW_VOLT_BAT (0x04 << 4)
|
||||
#define MAX77843_CHG_OVER_VOLT_BAT (0x05 << 4)
|
||||
#define MAX77843_CHG_OVER_CURRENT_BAT (0x06 << 4)
|
||||
|
||||
/* MAX77843 CHG_CNFG_00 register */
|
||||
#define MAX77843_CHG_DISABLE 0x00
|
||||
#define MAX77843_CHG_ENABLE 0x05
|
||||
#define MAX77843_CHG_MASK 0x01
|
||||
#define MAX77843_CHG_BUCK_MASK 0x04
|
||||
|
||||
/* MAX77843 CHG_CNFG_01 register */
|
||||
#define MAX77843_CHG_RESTART_THRESHOLD_100 0x00
|
||||
#define MAX77843_CHG_RESTART_THRESHOLD_150 0x10
|
||||
#define MAX77843_CHG_RESTART_THRESHOLD_200 0x20
|
||||
#define MAX77843_CHG_RESTART_THRESHOLD_DISABLE 0x30
|
||||
|
||||
/* MAX77843 CHG_CNFG_02 register */
|
||||
#define MAX77843_CHG_FAST_CHG_CURRENT_MIN 100000
|
||||
#define MAX77843_CHG_FAST_CHG_CURRENT_MAX 3150000
|
||||
#define MAX77843_CHG_FAST_CHG_CURRENT_STEP 50000
|
||||
#define MAX77843_CHG_FAST_CHG_CURRENT_MASK 0x3f
|
||||
#define MAX77843_CHG_OTG_ILIMIT_500 (0x00 << 6)
|
||||
#define MAX77843_CHG_OTG_ILIMIT_900 (0x01 << 6)
|
||||
#define MAX77843_CHG_OTG_ILIMIT_1200 (0x02 << 6)
|
||||
#define MAX77843_CHG_OTG_ILIMIT_1500 (0x03 << 6)
|
||||
#define MAX77843_CHG_OTG_ILIMIT_MASK 0xc0
|
||||
|
||||
/* MAX77843 CHG_CNFG_03 register */
|
||||
#define MAX77843_CHG_TOP_OFF_CURRENT_MIN 125000
|
||||
#define MAX77843_CHG_TOP_OFF_CURRENT_MAX 650000
|
||||
#define MAX77843_CHG_TOP_OFF_CURRENT_STEP 75000
|
||||
#define MAX77843_CHG_TOP_OFF_CURRENT_MASK 0x07
|
||||
|
||||
/* MAX77843 CHG_CNFG_06 register */
|
||||
#define MAX77843_CHG_WRITE_CAP_BLOCK 0x10
|
||||
#define MAX77843_CHG_WRITE_CAP_UNBLOCK 0x0C
|
||||
|
||||
/* MAX77843_CHG_CNFG_09_register */
|
||||
#define MAX77843_CHG_INPUT_CURRENT_LIMIT_MIN 100000
|
||||
#define MAX77843_CHG_INPUT_CURRENT_LIMIT_MAX 4000000
|
||||
#define MAX77843_CHG_INPUT_CURRENT_LIMIT_REF 3367000
|
||||
#define MAX77843_CHG_INPUT_CURRENT_LIMIT_STEP 33000
|
||||
|
||||
#define MAX77843_MUIC_ADC BIT(0)
|
||||
#define MAX77843_MUIC_ADCERROR BIT(2)
|
||||
#define MAX77843_MUIC_ADC1K BIT(3)
|
||||
|
||||
#define MAX77843_MUIC_CHGTYP BIT(0)
|
||||
#define MAX77843_MUIC_CHGDETRUN BIT(1)
|
||||
#define MAX77843_MUIC_DCDTMR BIT(2)
|
||||
#define MAX77843_MUIC_DXOVP BIT(3)
|
||||
#define MAX77843_MUIC_VBVOLT BIT(4)
|
||||
|
||||
#define MAX77843_MUIC_VBADC BIT(0)
|
||||
#define MAX77843_MUIC_VDNMON BIT(1)
|
||||
#define MAX77843_MUIC_DNRES BIT(2)
|
||||
#define MAX77843_MUIC_MPNACK BIT(3)
|
||||
#define MAX77843_MUIC_MRXBUFOW BIT(4)
|
||||
#define MAX77843_MUIC_MRXTRF BIT(5)
|
||||
#define MAX77843_MUIC_MRXPERR BIT(6)
|
||||
#define MAX77843_MUIC_MRXRDY BIT(7)
|
||||
|
||||
/* MAX77843 INTSRCMASK register */
|
||||
#define MAX77843_INTSRCMASK_CHGR 0
|
||||
#define MAX77843_INTSRCMASK_SYS 1
|
||||
#define MAX77843_INTSRCMASK_FG 2
|
||||
#define MAX77843_INTSRCMASK_MUIC 3
|
||||
|
||||
#define MAX77843_INTSRCMASK_CHGR_MASK BIT(MAX77843_INTSRCMASK_CHGR)
|
||||
#define MAX77843_INTSRCMASK_SYS_MASK BIT(MAX77843_INTSRCMASK_SYS)
|
||||
#define MAX77843_INTSRCMASK_FG_MASK BIT(MAX77843_INTSRCMASK_FG)
|
||||
#define MAX77843_INTSRCMASK_MUIC_MASK BIT(MAX77843_INTSRCMASK_MUIC)
|
||||
|
||||
#define MAX77843_INTSRC_MASK_MASK \
|
||||
(MAX77843_INTSRCMASK_MUIC_MASK | MAX77843_INTSRCMASK_FG_MASK | \
|
||||
MAX77843_INTSRCMASK_SYS_MASK | MAX77843_INTSRCMASK_CHGR_MASK)
|
||||
|
||||
/* MAX77843 STATUS register*/
|
||||
#define STATUS1_ADC_SHIFT 0
|
||||
#define STATUS1_ADCERROR_SHIFT 6
|
||||
#define STATUS1_ADC1K_SHIFT 7
|
||||
#define STATUS2_CHGTYP_SHIFT 0
|
||||
#define STATUS2_CHGDETRUN_SHIFT 3
|
||||
#define STATUS2_DCDTMR_SHIFT 4
|
||||
#define STATUS2_DXOVP_SHIFT 5
|
||||
#define STATUS2_VBVOLT_SHIFT 6
|
||||
#define STATUS3_VBADC_SHIFT 0
|
||||
#define STATUS3_VDNMON_SHIFT 4
|
||||
#define STATUS3_DNRES_SHIFT 5
|
||||
#define STATUS3_MPNACK_SHIFT 6
|
||||
|
||||
#define MAX77843_MUIC_STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
|
||||
#define MAX77843_MUIC_STATUS1_ADCERROR_MASK BIT(STATUS1_ADCERROR_SHIFT)
|
||||
#define MAX77843_MUIC_STATUS1_ADC1K_MASK BIT(STATUS1_ADC1K_SHIFT)
|
||||
#define MAX77843_MUIC_STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
|
||||
#define MAX77843_MUIC_STATUS2_CHGDETRUN_MASK BIT(STATUS2_CHGDETRUN_SHIFT)
|
||||
#define MAX77843_MUIC_STATUS2_DCDTMR_MASK BIT(STATUS2_DCDTMR_SHIFT)
|
||||
#define MAX77843_MUIC_STATUS2_DXOVP_MASK BIT(STATUS2_DXOVP_SHIFT)
|
||||
#define MAX77843_MUIC_STATUS2_VBVOLT_MASK BIT(STATUS2_VBVOLT_SHIFT)
|
||||
#define MAX77843_MUIC_STATUS3_VBADC_MASK (0xf << STATUS3_VBADC_SHIFT)
|
||||
#define MAX77843_MUIC_STATUS3_VDNMON_MASK BIT(STATUS3_VDNMON_SHIFT)
|
||||
#define MAX77843_MUIC_STATUS3_DNRES_MASK BIT(STATUS3_DNRES_SHIFT)
|
||||
#define MAX77843_MUIC_STATUS3_MPNACK_MASK BIT(STATUS3_MPNACK_SHIFT)
|
||||
|
||||
/* MAX77843 CONTROL register */
|
||||
#define CONTROL1_COMP1SW_SHIFT 0
|
||||
#define CONTROL1_COMP2SW_SHIFT 3
|
||||
#define CONTROL1_IDBEN_SHIFT 7
|
||||
#define CONTROL2_LOWPWR_SHIFT 0
|
||||
#define CONTROL2_ADCEN_SHIFT 1
|
||||
#define CONTROL2_CPEN_SHIFT 2
|
||||
#define CONTROL2_ACC_DET_SHIFT 5
|
||||
#define CONTROL2_USBCPINT_SHIFT 6
|
||||
#define CONTROL2_RCPS_SHIFT 7
|
||||
#define CONTROL3_JIGSET_SHIFT 0
|
||||
#define CONTROL4_ADCDBSET_SHIFT 0
|
||||
#define CONTROL4_USBAUTO_SHIFT 4
|
||||
#define CONTROL4_FCTAUTO_SHIFT 5
|
||||
#define CONTROL4_ADCMODE_SHIFT 6
|
||||
|
||||
#define MAX77843_MUIC_CONTROL1_COMP1SW_MASK (0x7 << CONTROL1_COMP1SW_SHIFT)
|
||||
#define MAX77843_MUIC_CONTROL1_COMP2SW_MASK (0x7 << CONTROL1_COMP2SW_SHIFT)
|
||||
#define MAX77843_MUIC_CONTROL1_IDBEN_MASK BIT(CONTROL1_IDBEN_SHIFT)
|
||||
#define MAX77843_MUIC_CONTROL2_LOWPWR_MASK BIT(CONTROL2_LOWPWR_SHIFT)
|
||||
#define MAX77843_MUIC_CONTROL2_ADCEN_MASK BIT(CONTROL2_ADCEN_SHIFT)
|
||||
#define MAX77843_MUIC_CONTROL2_CPEN_MASK BIT(CONTROL2_CPEN_SHIFT)
|
||||
#define MAX77843_MUIC_CONTROL2_ACC_DET_MASK BIT(CONTROL2_ACC_DET_SHIFT)
|
||||
#define MAX77843_MUIC_CONTROL2_USBCPINT_MASK BIT(CONTROL2_USBCPINT_SHIFT)
|
||||
#define MAX77843_MUIC_CONTROL2_RCPS_MASK BIT(CONTROL2_RCPS_SHIFT)
|
||||
#define MAX77843_MUIC_CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT)
|
||||
#define MAX77843_MUIC_CONTROL4_ADCDBSET_MASK (0x3 << CONTROL4_ADCDBSET_SHIFT)
|
||||
#define MAX77843_MUIC_CONTROL4_USBAUTO_MASK BIT(CONTROL4_USBAUTO_SHIFT)
|
||||
#define MAX77843_MUIC_CONTROL4_FCTAUTO_MASK BIT(CONTROL4_FCTAUTO_SHIFT)
|
||||
#define MAX77843_MUIC_CONTROL4_ADCMODE_MASK (0x3 << CONTROL4_ADCMODE_SHIFT)
|
||||
|
||||
/* MAX77843 switch port */
|
||||
#define COM_OPEN 0
|
||||
#define COM_USB 1
|
||||
#define COM_AUDIO 2
|
||||
#define COM_UART 3
|
||||
#define COM_AUX_USB 4
|
||||
#define COM_AUX_UART 5
|
||||
|
||||
#define CONTROL1_COM_SW \
|
||||
((MAX77843_MUIC_CONTROL1_COMP1SW_MASK | \
|
||||
MAX77843_MUIC_CONTROL1_COMP2SW_MASK))
|
||||
|
||||
#define CONTROL1_SW_OPEN \
|
||||
((COM_OPEN << CONTROL1_COMP1SW_SHIFT | \
|
||||
COM_OPEN << CONTROL1_COMP2SW_SHIFT))
|
||||
#define CONTROL1_SW_USB \
|
||||
((COM_USB << CONTROL1_COMP1SW_SHIFT | \
|
||||
COM_USB << CONTROL1_COMP2SW_SHIFT))
|
||||
#define CONTROL1_SW_AUDIO \
|
||||
((COM_AUDIO << CONTROL1_COMP1SW_SHIFT | \
|
||||
COM_AUDIO << CONTROL1_COMP2SW_SHIFT))
|
||||
#define CONTROL1_SW_UART \
|
||||
((COM_UART << CONTROL1_COMP1SW_SHIFT | \
|
||||
COM_UART << CONTROL1_COMP2SW_SHIFT))
|
||||
#define CONTROL1_SW_AUX_USB \
|
||||
((COM_AUX_USB << CONTROL1_COMP1SW_SHIFT | \
|
||||
COM_AUX_USB << CONTROL1_COMP2SW_SHIFT))
|
||||
#define CONTROL1_SW_AUX_UART \
|
||||
((COM_AUX_UART << CONTROL1_COMP1SW_SHIFT | \
|
||||
COM_AUX_UART << CONTROL1_COMP2SW_SHIFT))
|
||||
|
||||
#define MAX77843_DISABLE 0
|
||||
#define MAX77843_ENABLE 1
|
||||
|
||||
#define CONTROL4_AUTO_DISABLE \
|
||||
((MAX77843_DISABLE << CONTROL4_USBAUTO_SHIFT) | \
|
||||
(MAX77843_DISABLE << CONTROL4_FCTAUTO_SHIFT))
|
||||
#define CONTROL4_AUTO_ENABLE \
|
||||
((MAX77843_ENABLE << CONTROL4_USBAUTO_SHIFT) | \
|
||||
(MAX77843_ENABLE << CONTROL4_FCTAUTO_SHIFT))
|
||||
|
||||
/* MAX77843 SAFEOUT LDO Control register */
|
||||
#define SAFEOUTCTRL_SAFEOUT1_SHIFT 0
|
||||
#define SAFEOUTCTRL_SAFEOUT2_SHIFT 2
|
||||
#define SAFEOUTCTRL_ENSAFEOUT1_SHIFT 6
|
||||
#define SAFEOUTCTRL_ENSAFEOUT2_SHIFT 7
|
||||
|
||||
#define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT1 \
|
||||
BIT(SAFEOUTCTRL_ENSAFEOUT1_SHIFT)
|
||||
#define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT2 \
|
||||
BIT(SAFEOUTCTRL_ENSAFEOUT2_SHIFT)
|
||||
#define MAX77843_REG_SAFEOUTCTRL_SAFEOUT1_MASK \
|
||||
(0x3 << SAFEOUTCTRL_SAFEOUT1_SHIFT)
|
||||
#define MAX77843_REG_SAFEOUTCTRL_SAFEOUT2_MASK \
|
||||
(0x3 << SAFEOUTCTRL_SAFEOUT2_SHIFT)
|
||||
|
||||
struct max77843 {
|
||||
struct device *dev;
|
||||
|
||||
struct i2c_client *i2c;
|
||||
struct i2c_client *i2c_chg;
|
||||
struct i2c_client *i2c_fuel;
|
||||
struct i2c_client *i2c_muic;
|
||||
|
||||
struct regmap *regmap;
|
||||
struct regmap *regmap_chg;
|
||||
struct regmap *regmap_fuel;
|
||||
struct regmap *regmap_muic;
|
||||
|
||||
struct regmap_irq_chip_data *irq_data;
|
||||
struct regmap_irq_chip_data *irq_data_chg;
|
||||
struct regmap_irq_chip_data *irq_data_fuel;
|
||||
struct regmap_irq_chip_data *irq_data_muic;
|
||||
|
||||
int irq;
|
||||
};
|
||||
#endif /* __MAX77843_H__ */
|
||||
|
|
@ -24,7 +24,6 @@ extern int menelaus_set_vaux(unsigned int mV);
|
|||
extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
|
||||
extern int menelaus_set_slot_sel(int enable);
|
||||
extern int menelaus_get_slot_pin_states(void);
|
||||
extern int menelaus_set_vcore_sw(unsigned int mV);
|
||||
extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
|
||||
|
||||
#define EN_VPLL_SLEEP (1 << 7)
|
||||
|
|
@ -38,10 +37,4 @@ extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
|
|||
|
||||
extern int menelaus_set_regulator_sleep(int enable, u32 val);
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_MENELAUS)
|
||||
#define omap_has_menelaus() 1
|
||||
#else
|
||||
#define omap_has_menelaus() 0
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
64
include/linux/mfd/mt6397/core.h
Normal file
64
include/linux/mfd/mt6397/core.h
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* Copyright (c) 2014 MediaTek Inc.
|
||||
* Author: Flora Fu, MediaTek
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __MFD_MT6397_CORE_H__
|
||||
#define __MFD_MT6397_CORE_H__
|
||||
|
||||
enum mt6397_irq_numbers {
|
||||
MT6397_IRQ_SPKL_AB = 0,
|
||||
MT6397_IRQ_SPKR_AB,
|
||||
MT6397_IRQ_SPKL,
|
||||
MT6397_IRQ_SPKR,
|
||||
MT6397_IRQ_BAT_L,
|
||||
MT6397_IRQ_BAT_H,
|
||||
MT6397_IRQ_FG_BAT_L,
|
||||
MT6397_IRQ_FG_BAT_H,
|
||||
MT6397_IRQ_WATCHDOG,
|
||||
MT6397_IRQ_PWRKEY,
|
||||
MT6397_IRQ_THR_L,
|
||||
MT6397_IRQ_THR_H,
|
||||
MT6397_IRQ_VBATON_UNDET,
|
||||
MT6397_IRQ_BVALID_DET,
|
||||
MT6397_IRQ_CHRDET,
|
||||
MT6397_IRQ_OV,
|
||||
MT6397_IRQ_LDO,
|
||||
MT6397_IRQ_HOMEKEY,
|
||||
MT6397_IRQ_ACCDET,
|
||||
MT6397_IRQ_AUDIO,
|
||||
MT6397_IRQ_RTC,
|
||||
MT6397_IRQ_PWRKEY_RSTB,
|
||||
MT6397_IRQ_HDMI_SIFM,
|
||||
MT6397_IRQ_HDMI_CEC,
|
||||
MT6397_IRQ_VCA15,
|
||||
MT6397_IRQ_VSRMCA15,
|
||||
MT6397_IRQ_VCORE,
|
||||
MT6397_IRQ_VGPU,
|
||||
MT6397_IRQ_VIO18,
|
||||
MT6397_IRQ_VPCA7,
|
||||
MT6397_IRQ_VSRMCA7,
|
||||
MT6397_IRQ_VDRM,
|
||||
MT6397_IRQ_NR,
|
||||
};
|
||||
|
||||
struct mt6397_chip {
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
int irq;
|
||||
struct irq_domain *irq_domain;
|
||||
struct mutex irqlock;
|
||||
u16 irq_masks_cur[2];
|
||||
u16 irq_masks_cache[2];
|
||||
};
|
||||
|
||||
#endif /* __MFD_MT6397_CORE_H__ */
|
||||
362
include/linux/mfd/mt6397/registers.h
Normal file
362
include/linux/mfd/mt6397/registers.h
Normal file
|
|
@ -0,0 +1,362 @@
|
|||
/*
|
||||
* Copyright (c) 2014 MediaTek Inc.
|
||||
* Author: Flora Fu, MediaTek
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __MFD_MT6397_REGISTERS_H__
|
||||
#define __MFD_MT6397_REGISTERS_H__
|
||||
|
||||
/* PMIC Registers */
|
||||
#define MT6397_CID 0x0100
|
||||
#define MT6397_TOP_CKPDN 0x0102
|
||||
#define MT6397_TOP_CKPDN_SET 0x0104
|
||||
#define MT6397_TOP_CKPDN_CLR 0x0106
|
||||
#define MT6397_TOP_CKPDN2 0x0108
|
||||
#define MT6397_TOP_CKPDN2_SET 0x010A
|
||||
#define MT6397_TOP_CKPDN2_CLR 0x010C
|
||||
#define MT6397_TOP_GPIO_CKPDN 0x010E
|
||||
#define MT6397_TOP_RST_CON 0x0114
|
||||
#define MT6397_WRP_CKPDN 0x011A
|
||||
#define MT6397_WRP_RST_CON 0x0120
|
||||
#define MT6397_TOP_RST_MISC 0x0126
|
||||
#define MT6397_TOP_CKCON1 0x0128
|
||||
#define MT6397_TOP_CKCON2 0x012A
|
||||
#define MT6397_TOP_CKTST1 0x012C
|
||||
#define MT6397_TOP_CKTST2 0x012E
|
||||
#define MT6397_OC_DEG_EN 0x0130
|
||||
#define MT6397_OC_CTL0 0x0132
|
||||
#define MT6397_OC_CTL1 0x0134
|
||||
#define MT6397_OC_CTL2 0x0136
|
||||
#define MT6397_INT_RSV 0x0138
|
||||
#define MT6397_TEST_CON0 0x013A
|
||||
#define MT6397_TEST_CON1 0x013C
|
||||
#define MT6397_STATUS0 0x013E
|
||||
#define MT6397_STATUS1 0x0140
|
||||
#define MT6397_PGSTATUS 0x0142
|
||||
#define MT6397_CHRSTATUS 0x0144
|
||||
#define MT6397_OCSTATUS0 0x0146
|
||||
#define MT6397_OCSTATUS1 0x0148
|
||||
#define MT6397_OCSTATUS2 0x014A
|
||||
#define MT6397_HDMI_PAD_IE 0x014C
|
||||
#define MT6397_TEST_OUT_L 0x014E
|
||||
#define MT6397_TEST_OUT_H 0x0150
|
||||
#define MT6397_TDSEL_CON 0x0152
|
||||
#define MT6397_RDSEL_CON 0x0154
|
||||
#define MT6397_GPIO_SMT_CON0 0x0156
|
||||
#define MT6397_GPIO_SMT_CON1 0x0158
|
||||
#define MT6397_GPIO_SMT_CON2 0x015A
|
||||
#define MT6397_GPIO_SMT_CON3 0x015C
|
||||
#define MT6397_DRV_CON0 0x015E
|
||||
#define MT6397_DRV_CON1 0x0160
|
||||
#define MT6397_DRV_CON2 0x0162
|
||||
#define MT6397_DRV_CON3 0x0164
|
||||
#define MT6397_DRV_CON4 0x0166
|
||||
#define MT6397_DRV_CON5 0x0168
|
||||
#define MT6397_DRV_CON6 0x016A
|
||||
#define MT6397_DRV_CON7 0x016C
|
||||
#define MT6397_DRV_CON8 0x016E
|
||||
#define MT6397_DRV_CON9 0x0170
|
||||
#define MT6397_DRV_CON10 0x0172
|
||||
#define MT6397_DRV_CON11 0x0174
|
||||
#define MT6397_DRV_CON12 0x0176
|
||||
#define MT6397_INT_CON0 0x0178
|
||||
#define MT6397_INT_CON1 0x017E
|
||||
#define MT6397_INT_STATUS0 0x0184
|
||||
#define MT6397_INT_STATUS1 0x0186
|
||||
#define MT6397_FQMTR_CON0 0x0188
|
||||
#define MT6397_FQMTR_CON1 0x018A
|
||||
#define MT6397_FQMTR_CON2 0x018C
|
||||
#define MT6397_EFUSE_DOUT_0_15 0x01C4
|
||||
#define MT6397_EFUSE_DOUT_16_31 0x01C6
|
||||
#define MT6397_EFUSE_DOUT_32_47 0x01C8
|
||||
#define MT6397_EFUSE_DOUT_48_63 0x01CA
|
||||
#define MT6397_SPI_CON 0x01CC
|
||||
#define MT6397_TOP_CKPDN3 0x01CE
|
||||
#define MT6397_TOP_CKCON3 0x01D4
|
||||
#define MT6397_EFUSE_DOUT_64_79 0x01D6
|
||||
#define MT6397_EFUSE_DOUT_80_95 0x01D8
|
||||
#define MT6397_EFUSE_DOUT_96_111 0x01DA
|
||||
#define MT6397_EFUSE_DOUT_112_127 0x01DC
|
||||
#define MT6397_EFUSE_DOUT_128_143 0x01DE
|
||||
#define MT6397_EFUSE_DOUT_144_159 0x01E0
|
||||
#define MT6397_EFUSE_DOUT_160_175 0x01E2
|
||||
#define MT6397_EFUSE_DOUT_176_191 0x01E4
|
||||
#define MT6397_EFUSE_DOUT_192_207 0x01E6
|
||||
#define MT6397_EFUSE_DOUT_208_223 0x01E8
|
||||
#define MT6397_EFUSE_DOUT_224_239 0x01EA
|
||||
#define MT6397_EFUSE_DOUT_240_255 0x01EC
|
||||
#define MT6397_EFUSE_DOUT_256_271 0x01EE
|
||||
#define MT6397_EFUSE_DOUT_272_287 0x01F0
|
||||
#define MT6397_EFUSE_DOUT_288_300 0x01F2
|
||||
#define MT6397_EFUSE_DOUT_304_319 0x01F4
|
||||
#define MT6397_BUCK_CON0 0x0200
|
||||
#define MT6397_BUCK_CON1 0x0202
|
||||
#define MT6397_BUCK_CON2 0x0204
|
||||
#define MT6397_BUCK_CON3 0x0206
|
||||
#define MT6397_BUCK_CON4 0x0208
|
||||
#define MT6397_BUCK_CON5 0x020A
|
||||
#define MT6397_BUCK_CON6 0x020C
|
||||
#define MT6397_BUCK_CON7 0x020E
|
||||
#define MT6397_BUCK_CON8 0x0210
|
||||
#define MT6397_BUCK_CON9 0x0212
|
||||
#define MT6397_VCA15_CON0 0x0214
|
||||
#define MT6397_VCA15_CON1 0x0216
|
||||
#define MT6397_VCA15_CON2 0x0218
|
||||
#define MT6397_VCA15_CON3 0x021A
|
||||
#define MT6397_VCA15_CON4 0x021C
|
||||
#define MT6397_VCA15_CON5 0x021E
|
||||
#define MT6397_VCA15_CON6 0x0220
|
||||
#define MT6397_VCA15_CON7 0x0222
|
||||
#define MT6397_VCA15_CON8 0x0224
|
||||
#define MT6397_VCA15_CON9 0x0226
|
||||
#define MT6397_VCA15_CON10 0x0228
|
||||
#define MT6397_VCA15_CON11 0x022A
|
||||
#define MT6397_VCA15_CON12 0x022C
|
||||
#define MT6397_VCA15_CON13 0x022E
|
||||
#define MT6397_VCA15_CON14 0x0230
|
||||
#define MT6397_VCA15_CON15 0x0232
|
||||
#define MT6397_VCA15_CON16 0x0234
|
||||
#define MT6397_VCA15_CON17 0x0236
|
||||
#define MT6397_VCA15_CON18 0x0238
|
||||
#define MT6397_VSRMCA15_CON0 0x023A
|
||||
#define MT6397_VSRMCA15_CON1 0x023C
|
||||
#define MT6397_VSRMCA15_CON2 0x023E
|
||||
#define MT6397_VSRMCA15_CON3 0x0240
|
||||
#define MT6397_VSRMCA15_CON4 0x0242
|
||||
#define MT6397_VSRMCA15_CON5 0x0244
|
||||
#define MT6397_VSRMCA15_CON6 0x0246
|
||||
#define MT6397_VSRMCA15_CON7 0x0248
|
||||
#define MT6397_VSRMCA15_CON8 0x024A
|
||||
#define MT6397_VSRMCA15_CON9 0x024C
|
||||
#define MT6397_VSRMCA15_CON10 0x024E
|
||||
#define MT6397_VSRMCA15_CON11 0x0250
|
||||
#define MT6397_VSRMCA15_CON12 0x0252
|
||||
#define MT6397_VSRMCA15_CON13 0x0254
|
||||
#define MT6397_VSRMCA15_CON14 0x0256
|
||||
#define MT6397_VSRMCA15_CON15 0x0258
|
||||
#define MT6397_VSRMCA15_CON16 0x025A
|
||||
#define MT6397_VSRMCA15_CON17 0x025C
|
||||
#define MT6397_VSRMCA15_CON18 0x025E
|
||||
#define MT6397_VSRMCA15_CON19 0x0260
|
||||
#define MT6397_VSRMCA15_CON20 0x0262
|
||||
#define MT6397_VSRMCA15_CON21 0x0264
|
||||
#define MT6397_VCORE_CON0 0x0266
|
||||
#define MT6397_VCORE_CON1 0x0268
|
||||
#define MT6397_VCORE_CON2 0x026A
|
||||
#define MT6397_VCORE_CON3 0x026C
|
||||
#define MT6397_VCORE_CON4 0x026E
|
||||
#define MT6397_VCORE_CON5 0x0270
|
||||
#define MT6397_VCORE_CON6 0x0272
|
||||
#define MT6397_VCORE_CON7 0x0274
|
||||
#define MT6397_VCORE_CON8 0x0276
|
||||
#define MT6397_VCORE_CON9 0x0278
|
||||
#define MT6397_VCORE_CON10 0x027A
|
||||
#define MT6397_VCORE_CON11 0x027C
|
||||
#define MT6397_VCORE_CON12 0x027E
|
||||
#define MT6397_VCORE_CON13 0x0280
|
||||
#define MT6397_VCORE_CON14 0x0282
|
||||
#define MT6397_VCORE_CON15 0x0284
|
||||
#define MT6397_VCORE_CON16 0x0286
|
||||
#define MT6397_VCORE_CON17 0x0288
|
||||
#define MT6397_VCORE_CON18 0x028A
|
||||
#define MT6397_VGPU_CON0 0x028C
|
||||
#define MT6397_VGPU_CON1 0x028E
|
||||
#define MT6397_VGPU_CON2 0x0290
|
||||
#define MT6397_VGPU_CON3 0x0292
|
||||
#define MT6397_VGPU_CON4 0x0294
|
||||
#define MT6397_VGPU_CON5 0x0296
|
||||
#define MT6397_VGPU_CON6 0x0298
|
||||
#define MT6397_VGPU_CON7 0x029A
|
||||
#define MT6397_VGPU_CON8 0x029C
|
||||
#define MT6397_VGPU_CON9 0x029E
|
||||
#define MT6397_VGPU_CON10 0x02A0
|
||||
#define MT6397_VGPU_CON11 0x02A2
|
||||
#define MT6397_VGPU_CON12 0x02A4
|
||||
#define MT6397_VGPU_CON13 0x02A6
|
||||
#define MT6397_VGPU_CON14 0x02A8
|
||||
#define MT6397_VGPU_CON15 0x02AA
|
||||
#define MT6397_VGPU_CON16 0x02AC
|
||||
#define MT6397_VGPU_CON17 0x02AE
|
||||
#define MT6397_VGPU_CON18 0x02B0
|
||||
#define MT6397_VIO18_CON0 0x0300
|
||||
#define MT6397_VIO18_CON1 0x0302
|
||||
#define MT6397_VIO18_CON2 0x0304
|
||||
#define MT6397_VIO18_CON3 0x0306
|
||||
#define MT6397_VIO18_CON4 0x0308
|
||||
#define MT6397_VIO18_CON5 0x030A
|
||||
#define MT6397_VIO18_CON6 0x030C
|
||||
#define MT6397_VIO18_CON7 0x030E
|
||||
#define MT6397_VIO18_CON8 0x0310
|
||||
#define MT6397_VIO18_CON9 0x0312
|
||||
#define MT6397_VIO18_CON10 0x0314
|
||||
#define MT6397_VIO18_CON11 0x0316
|
||||
#define MT6397_VIO18_CON12 0x0318
|
||||
#define MT6397_VIO18_CON13 0x031A
|
||||
#define MT6397_VIO18_CON14 0x031C
|
||||
#define MT6397_VIO18_CON15 0x031E
|
||||
#define MT6397_VIO18_CON16 0x0320
|
||||
#define MT6397_VIO18_CON17 0x0322
|
||||
#define MT6397_VIO18_CON18 0x0324
|
||||
#define MT6397_VPCA7_CON0 0x0326
|
||||
#define MT6397_VPCA7_CON1 0x0328
|
||||
#define MT6397_VPCA7_CON2 0x032A
|
||||
#define MT6397_VPCA7_CON3 0x032C
|
||||
#define MT6397_VPCA7_CON4 0x032E
|
||||
#define MT6397_VPCA7_CON5 0x0330
|
||||
#define MT6397_VPCA7_CON6 0x0332
|
||||
#define MT6397_VPCA7_CON7 0x0334
|
||||
#define MT6397_VPCA7_CON8 0x0336
|
||||
#define MT6397_VPCA7_CON9 0x0338
|
||||
#define MT6397_VPCA7_CON10 0x033A
|
||||
#define MT6397_VPCA7_CON11 0x033C
|
||||
#define MT6397_VPCA7_CON12 0x033E
|
||||
#define MT6397_VPCA7_CON13 0x0340
|
||||
#define MT6397_VPCA7_CON14 0x0342
|
||||
#define MT6397_VPCA7_CON15 0x0344
|
||||
#define MT6397_VPCA7_CON16 0x0346
|
||||
#define MT6397_VPCA7_CON17 0x0348
|
||||
#define MT6397_VPCA7_CON18 0x034A
|
||||
#define MT6397_VSRMCA7_CON0 0x034C
|
||||
#define MT6397_VSRMCA7_CON1 0x034E
|
||||
#define MT6397_VSRMCA7_CON2 0x0350
|
||||
#define MT6397_VSRMCA7_CON3 0x0352
|
||||
#define MT6397_VSRMCA7_CON4 0x0354
|
||||
#define MT6397_VSRMCA7_CON5 0x0356
|
||||
#define MT6397_VSRMCA7_CON6 0x0358
|
||||
#define MT6397_VSRMCA7_CON7 0x035A
|
||||
#define MT6397_VSRMCA7_CON8 0x035C
|
||||
#define MT6397_VSRMCA7_CON9 0x035E
|
||||
#define MT6397_VSRMCA7_CON10 0x0360
|
||||
#define MT6397_VSRMCA7_CON11 0x0362
|
||||
#define MT6397_VSRMCA7_CON12 0x0364
|
||||
#define MT6397_VSRMCA7_CON13 0x0366
|
||||
#define MT6397_VSRMCA7_CON14 0x0368
|
||||
#define MT6397_VSRMCA7_CON15 0x036A
|
||||
#define MT6397_VSRMCA7_CON16 0x036C
|
||||
#define MT6397_VSRMCA7_CON17 0x036E
|
||||
#define MT6397_VSRMCA7_CON18 0x0370
|
||||
#define MT6397_VSRMCA7_CON19 0x0372
|
||||
#define MT6397_VSRMCA7_CON20 0x0374
|
||||
#define MT6397_VSRMCA7_CON21 0x0376
|
||||
#define MT6397_VDRM_CON0 0x0378
|
||||
#define MT6397_VDRM_CON1 0x037A
|
||||
#define MT6397_VDRM_CON2 0x037C
|
||||
#define MT6397_VDRM_CON3 0x037E
|
||||
#define MT6397_VDRM_CON4 0x0380
|
||||
#define MT6397_VDRM_CON5 0x0382
|
||||
#define MT6397_VDRM_CON6 0x0384
|
||||
#define MT6397_VDRM_CON7 0x0386
|
||||
#define MT6397_VDRM_CON8 0x0388
|
||||
#define MT6397_VDRM_CON9 0x038A
|
||||
#define MT6397_VDRM_CON10 0x038C
|
||||
#define MT6397_VDRM_CON11 0x038E
|
||||
#define MT6397_VDRM_CON12 0x0390
|
||||
#define MT6397_VDRM_CON13 0x0392
|
||||
#define MT6397_VDRM_CON14 0x0394
|
||||
#define MT6397_VDRM_CON15 0x0396
|
||||
#define MT6397_VDRM_CON16 0x0398
|
||||
#define MT6397_VDRM_CON17 0x039A
|
||||
#define MT6397_VDRM_CON18 0x039C
|
||||
#define MT6397_BUCK_K_CON0 0x039E
|
||||
#define MT6397_BUCK_K_CON1 0x03A0
|
||||
#define MT6397_ANALDO_CON0 0x0400
|
||||
#define MT6397_ANALDO_CON1 0x0402
|
||||
#define MT6397_ANALDO_CON2 0x0404
|
||||
#define MT6397_ANALDO_CON3 0x0406
|
||||
#define MT6397_ANALDO_CON4 0x0408
|
||||
#define MT6397_ANALDO_CON5 0x040A
|
||||
#define MT6397_ANALDO_CON6 0x040C
|
||||
#define MT6397_ANALDO_CON7 0x040E
|
||||
#define MT6397_DIGLDO_CON0 0x0410
|
||||
#define MT6397_DIGLDO_CON1 0x0412
|
||||
#define MT6397_DIGLDO_CON2 0x0414
|
||||
#define MT6397_DIGLDO_CON3 0x0416
|
||||
#define MT6397_DIGLDO_CON4 0x0418
|
||||
#define MT6397_DIGLDO_CON5 0x041A
|
||||
#define MT6397_DIGLDO_CON6 0x041C
|
||||
#define MT6397_DIGLDO_CON7 0x041E
|
||||
#define MT6397_DIGLDO_CON8 0x0420
|
||||
#define MT6397_DIGLDO_CON9 0x0422
|
||||
#define MT6397_DIGLDO_CON10 0x0424
|
||||
#define MT6397_DIGLDO_CON11 0x0426
|
||||
#define MT6397_DIGLDO_CON12 0x0428
|
||||
#define MT6397_DIGLDO_CON13 0x042A
|
||||
#define MT6397_DIGLDO_CON14 0x042C
|
||||
#define MT6397_DIGLDO_CON15 0x042E
|
||||
#define MT6397_DIGLDO_CON16 0x0430
|
||||
#define MT6397_DIGLDO_CON17 0x0432
|
||||
#define MT6397_DIGLDO_CON18 0x0434
|
||||
#define MT6397_DIGLDO_CON19 0x0436
|
||||
#define MT6397_DIGLDO_CON20 0x0438
|
||||
#define MT6397_DIGLDO_CON21 0x043A
|
||||
#define MT6397_DIGLDO_CON22 0x043C
|
||||
#define MT6397_DIGLDO_CON23 0x043E
|
||||
#define MT6397_DIGLDO_CON24 0x0440
|
||||
#define MT6397_DIGLDO_CON25 0x0442
|
||||
#define MT6397_DIGLDO_CON26 0x0444
|
||||
#define MT6397_DIGLDO_CON27 0x0446
|
||||
#define MT6397_DIGLDO_CON28 0x0448
|
||||
#define MT6397_DIGLDO_CON29 0x044A
|
||||
#define MT6397_DIGLDO_CON30 0x044C
|
||||
#define MT6397_DIGLDO_CON31 0x044E
|
||||
#define MT6397_DIGLDO_CON32 0x0450
|
||||
#define MT6397_DIGLDO_CON33 0x045A
|
||||
#define MT6397_SPK_CON0 0x0600
|
||||
#define MT6397_SPK_CON1 0x0602
|
||||
#define MT6397_SPK_CON2 0x0604
|
||||
#define MT6397_SPK_CON3 0x0606
|
||||
#define MT6397_SPK_CON4 0x0608
|
||||
#define MT6397_SPK_CON5 0x060A
|
||||
#define MT6397_SPK_CON6 0x060C
|
||||
#define MT6397_SPK_CON7 0x060E
|
||||
#define MT6397_SPK_CON8 0x0610
|
||||
#define MT6397_SPK_CON9 0x0612
|
||||
#define MT6397_SPK_CON10 0x0614
|
||||
#define MT6397_SPK_CON11 0x0616
|
||||
#define MT6397_AUDDAC_CON0 0x0700
|
||||
#define MT6397_AUDBUF_CFG0 0x0702
|
||||
#define MT6397_AUDBUF_CFG1 0x0704
|
||||
#define MT6397_AUDBUF_CFG2 0x0706
|
||||
#define MT6397_AUDBUF_CFG3 0x0708
|
||||
#define MT6397_AUDBUF_CFG4 0x070A
|
||||
#define MT6397_IBIASDIST_CFG0 0x070C
|
||||
#define MT6397_AUDACCDEPOP_CFG0 0x070E
|
||||
#define MT6397_AUD_IV_CFG0 0x0710
|
||||
#define MT6397_AUDCLKGEN_CFG0 0x0712
|
||||
#define MT6397_AUDLDO_CFG0 0x0714
|
||||
#define MT6397_AUDLDO_CFG1 0x0716
|
||||
#define MT6397_AUDNVREGGLB_CFG0 0x0718
|
||||
#define MT6397_AUD_NCP0 0x071A
|
||||
#define MT6397_AUDPREAMP_CON0 0x071C
|
||||
#define MT6397_AUDADC_CON0 0x071E
|
||||
#define MT6397_AUDADC_CON1 0x0720
|
||||
#define MT6397_AUDADC_CON2 0x0722
|
||||
#define MT6397_AUDADC_CON3 0x0724
|
||||
#define MT6397_AUDADC_CON4 0x0726
|
||||
#define MT6397_AUDADC_CON5 0x0728
|
||||
#define MT6397_AUDADC_CON6 0x072A
|
||||
#define MT6397_AUDDIGMI_CON0 0x072C
|
||||
#define MT6397_AUDLSBUF_CON0 0x072E
|
||||
#define MT6397_AUDLSBUF_CON1 0x0730
|
||||
#define MT6397_AUDENCSPARE_CON0 0x0732
|
||||
#define MT6397_AUDENCCLKSQ_CON0 0x0734
|
||||
#define MT6397_AUDPREAMPGAIN_CON0 0x0736
|
||||
#define MT6397_ZCD_CON0 0x0738
|
||||
#define MT6397_ZCD_CON1 0x073A
|
||||
#define MT6397_ZCD_CON2 0x073C
|
||||
#define MT6397_ZCD_CON3 0x073E
|
||||
#define MT6397_ZCD_CON4 0x0740
|
||||
#define MT6397_ZCD_CON5 0x0742
|
||||
#define MT6397_NCP_CLKDIV_CON0 0x0744
|
||||
#define MT6397_NCP_CLKDIV_CON1 0x0746
|
||||
|
||||
#endif /* __MFD_MT6397_REGISTERS_H__ */
|
||||
|
|
@ -156,6 +156,9 @@ enum rk808_reg {
|
|||
#define BUCK2_RATE_MASK (3 << 3)
|
||||
#define MASK_ALL 0xff
|
||||
|
||||
#define BUCK_UV_ACT_MASK 0x0f
|
||||
#define BUCK_UV_ACT_DISABLE 0
|
||||
|
||||
#define SWITCH2_EN BIT(6)
|
||||
#define SWITCH1_EN BIT(5)
|
||||
#define DEV_OFF_RST BIT(3)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -58,13 +58,7 @@ enum sec_device_type {
|
|||
* @irq_base: Base IRQ number for device, required for IRQs
|
||||
* @irq: Generic IRQ number for device
|
||||
* @irq_data: Runtime data structure for IRQ controller
|
||||
* @ono: Power onoff IRQ number for s5m87xx
|
||||
* @wakeup: Whether or not this is a wakeup device
|
||||
* @wtsr_smpl: Whether or not to enable in RTC driver the Watchdog
|
||||
* Timer Software Reset (registers set to default value
|
||||
* after PWRHOLD falling) and Sudden Momentary Power Loss
|
||||
* (PMIC will enter power on sequence after short drop in
|
||||
* VBATT voltage).
|
||||
*/
|
||||
struct sec_pmic_dev {
|
||||
struct device *dev;
|
||||
|
|
@ -77,9 +71,7 @@ struct sec_pmic_dev {
|
|||
int irq;
|
||||
struct regmap_irq_chip_data *irq_data;
|
||||
|
||||
int ono;
|
||||
bool wakeup;
|
||||
bool wtsr_smpl;
|
||||
};
|
||||
|
||||
int sec_irq_init(struct sec_pmic_dev *sec_pmic);
|
||||
|
|
@ -95,7 +87,6 @@ struct sec_platform_data {
|
|||
int irq_base;
|
||||
int (*cfg_pmic_irq)(void);
|
||||
|
||||
int ono;
|
||||
bool wakeup;
|
||||
bool buck_voltage_lock;
|
||||
|
||||
|
|
|
|||
|
|
@ -74,8 +74,8 @@ enum s2mps11_irq {
|
|||
S2MPS11_IRQ_MRB,
|
||||
|
||||
S2MPS11_IRQ_RTC60S,
|
||||
S2MPS11_IRQ_RTCA0,
|
||||
S2MPS11_IRQ_RTCA1,
|
||||
S2MPS11_IRQ_RTCA0,
|
||||
S2MPS11_IRQ_SMPL,
|
||||
S2MPS11_IRQ_RTC1S,
|
||||
S2MPS11_IRQ_WTSR,
|
||||
|
|
|
|||
31
include/linux/mfd/sky81452.h
Normal file
31
include/linux/mfd/sky81452.h
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* sky81452.h SKY81452 MFD driver
|
||||
*
|
||||
* Copyright 2014 Skyworks Solutions Inc.
|
||||
* Author : Gyungoh Yoo <jack.yoo@skyworksinc.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _SKY81452_H
|
||||
#define _SKY81452_H
|
||||
|
||||
#include <linux/platform_data/sky81452-backlight.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
|
||||
struct sky81452_platform_data {
|
||||
struct sky81452_bl_platform_data *bl_pdata;
|
||||
struct regulator_init_data *regulator_init_data;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -128,6 +128,7 @@
|
|||
|
||||
/* Sequencer Status */
|
||||
#define SEQ_STATUS BIT(5)
|
||||
#define CHARGE_STEP 0x11
|
||||
|
||||
#define ADC_CLK 3000000
|
||||
#define TOTAL_STEPS 16
|
||||
|
|
|
|||
46
include/linux/platform_data/sky81452-backlight.h
Normal file
46
include/linux/platform_data/sky81452-backlight.h
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* sky81452.h SKY81452 backlight driver
|
||||
*
|
||||
* Copyright 2014 Skyworks Solutions Inc.
|
||||
* Author : Gyungoh Yoo <jack.yoo@skyworksinc.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _SKY81452_BACKLIGHT_H
|
||||
#define _SKY81452_BACKLIGHT_H
|
||||
|
||||
/**
|
||||
* struct sky81452_platform_data
|
||||
* @name: backlight driver name.
|
||||
If it is not defined, default name is lcd-backlight.
|
||||
* @gpio_enable:GPIO number which control EN pin
|
||||
* @enable: Enable mask for current sink channel 1, 2, 3, 4, 5 and 6.
|
||||
* @ignore_pwm: true if DPWMI should be ignored.
|
||||
* @dpwm_mode: true is DPWM dimming mode, otherwise Analog dimming mode.
|
||||
* @phase_shift:true is phase shift mode.
|
||||
* @short_detecion_threshold: It should be one of 4, 5, 6 and 7V.
|
||||
* @boost_current_limit: It should be one of 2300, 2750mA.
|
||||
*/
|
||||
struct sky81452_bl_platform_data {
|
||||
const char *name;
|
||||
int gpio_enable;
|
||||
unsigned int enable;
|
||||
bool ignore_pwm;
|
||||
bool dpwm_mode;
|
||||
bool phase_shift;
|
||||
unsigned int short_detection_threshold;
|
||||
unsigned int boost_current_limit;
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue