mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 11:41:38 -04:00
gpio: Move irqdomain into struct gpio_irq_chip
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <[email protected]> Acked-by: Grygorii Strashko <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
This commit is contained in:
parent
da80ff81a8
commit
f0fbe7bce7
56 changed files with 78 additions and 71 deletions
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@ -383,7 +383,7 @@ static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
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/* FIXME: no clue why the code looks up the type here */
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type = pc->irq_type[gpio];
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generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irqdomain,
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generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.irqdomain,
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gpio));
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}
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}
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@ -665,7 +665,7 @@ static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
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enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
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const char *fname = bcm2835_functions[fsel];
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int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
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int irq = irq_find_mapping(chip->irqdomain, offset);
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int irq = irq_find_mapping(chip->irq.domain, offset);
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seq_printf(s, "function %s in %s; irq %d (%s)",
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fname, value ? "hi" : "lo",
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@ -172,7 +172,7 @@ static void iproc_gpio_irq_handler(struct irq_desc *desc)
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for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
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unsigned pin = NGPIOS_PER_BANK * i + bit;
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int child_irq = irq_find_mapping(gc->irqdomain, pin);
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int child_irq = irq_find_mapping(gc->irq.domain, pin);
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/*
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* Clear the interrupt before invoking the
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@ -1627,7 +1627,7 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
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pending = readl(reg);
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raw_spin_unlock(&vg->lock);
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for_each_set_bit(pin, &pending, 32) {
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virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
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virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
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generic_handle_irq(virq);
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}
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}
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@ -1523,7 +1523,7 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
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unsigned irq, offset;
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offset = pctrl->intr_lines[intr_line];
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irq = irq_find_mapping(gc->irqdomain, offset);
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irq = irq_find_mapping(gc->irq.domain, offset);
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generic_handle_irq(irq);
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}
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@ -1005,7 +1005,7 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
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if (padno >= community->npins)
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break;
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irq = irq_find_mapping(gc->irqdomain,
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irq = irq_find_mapping(gc->irq.domain,
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community->pin_base + padno);
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generic_handle_irq(irq);
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@ -592,7 +592,7 @@ static void armada_37xx_irq_handler(struct irq_desc *desc)
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
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struct irq_domain *d = gc->irqdomain;
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struct irq_domain *d = gc->irq.domain;
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int i;
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chained_irq_enter(chip, desc);
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@ -413,7 +413,7 @@ nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
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u32 falling = nmk_chip->fimsc & BIT(offset);
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u32 rising = nmk_chip->rimsc & BIT(offset);
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int gpio = nmk_chip->chip.base + offset;
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int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset);
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int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset);
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struct irq_data *d = irq_get_irq_data(irq);
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if (!rising && !falling)
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@ -815,7 +815,7 @@ static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status)
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while (status) {
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int bit = __ffs(status);
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generic_handle_irq(irq_find_mapping(chip->irqdomain, bit));
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generic_handle_irq(irq_find_mapping(chip->irq.domain, bit));
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status &= ~BIT(bit);
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}
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@ -532,7 +532,7 @@ static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
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regval = readl(regs + i);
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if (!(regval & PIN_IRQ_PENDING))
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continue;
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irq = irq_find_mapping(gc->irqdomain, irqnr + i);
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irq = irq_find_mapping(gc->irq.domain, irqnr + i);
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generic_handle_irq(irq);
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/* Clear interrupt */
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writel(regval, regs + i);
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@ -1603,7 +1603,7 @@ static void gpio_irq_handler(struct irq_desc *desc)
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for_each_set_bit(n, &isr, BITS_PER_LONG) {
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generic_handle_irq(irq_find_mapping(
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gpio_chip->irqdomain, n));
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gpio_chip->irq.domain, n));
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}
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}
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chained_irq_exit(chip, desc);
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@ -517,7 +517,7 @@ static void u300_gpio_irq_handler(struct irq_desc *desc)
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for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
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int offset = pinoffset + irqoffset;
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int pin_irq = irq_find_mapping(chip->irqdomain, offset);
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int pin_irq = irq_find_mapping(chip->irq.domain, offset);
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dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
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pin_irq, offset);
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@ -537,7 +537,7 @@ static irqreturn_t mcp23s08_irq(int irq, void *data)
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((gpio_bit_changed || intcap_changed) &&
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(BIT(i) & mcp->irq_fall) && !gpio_set) ||
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defval_changed) {
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child_irq = irq_find_mapping(mcp->chip.irqdomain, i);
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child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
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handle_nested_irq(child_irq);
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}
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}
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@ -1064,7 +1064,7 @@ static void oxnas_gpio_irq_handler(struct irq_desc *desc)
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stat = readl(bank->reg_base + IRQ_PENDING);
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for_each_set_bit(pin, &stat, BITS_PER_LONG)
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generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin));
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generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
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chained_irq_exit(chip, desc);
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}
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@ -2106,7 +2106,7 @@ static void pic32_gpio_irq_handler(struct irq_desc *desc)
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pending = pic32_gpio_get_pending(gc, stat);
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for_each_set_bit(pin, &pending, BITS_PER_LONG)
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generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin));
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generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
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chained_irq_exit(chip, desc);
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}
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@ -1307,7 +1307,7 @@ static void pistachio_gpio_irq_handler(struct irq_desc *desc)
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pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) &
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gpio_readl(bank, GPIO_INTERRUPT_EN);
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for_each_set_bit(pin, &pending, 16)
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generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin));
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generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
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chained_irq_exit(chip, desc);
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}
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@ -1408,7 +1408,7 @@ static void __gpio_irq_handler(struct st_gpio_bank *bank)
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continue;
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}
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generic_handle_irq(irq_find_mapping(bank->gpio_chip.irqdomain, n));
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generic_handle_irq(irq_find_mapping(bank->gpio_chip.irq.domain, n));
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}
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}
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}
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@ -561,7 +561,7 @@ static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
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status = val;
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for_each_set_bit(n, &status, pctl->data->ngpios)
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handle_nested_irq(irq_find_mapping(pctl->gpio.irqdomain, n));
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handle_nested_irq(irq_find_mapping(pctl->gpio.irq.domain, n));
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return IRQ_HANDLED;
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}
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@ -795,7 +795,7 @@ static void msm_gpio_irq_handler(struct irq_desc *desc)
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g = &pctrl->soc->groups[i];
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val = readl(pctrl->regs + g->intr_status_reg);
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if (val & BIT(g->intr_status_bit)) {
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irq_pin = irq_find_mapping(gc->irqdomain, i);
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irq_pin = irq_find_mapping(gc->irq.domain, i);
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generic_handle_irq(irq_pin);
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handled++;
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}
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@ -5820,7 +5820,7 @@ static void atlas7_gpio_handle_irq(struct irq_desc *desc)
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__func__, gc->label,
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bank->gpio_offset + pin_in_bank);
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generic_handle_irq(
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irq_find_mapping(gc->irqdomain,
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irq_find_mapping(gc->irq.domain,
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bank->gpio_offset + pin_in_bank));
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}
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@ -587,7 +587,7 @@ static void sirfsoc_gpio_handle_irq(struct irq_desc *desc)
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if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
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pr_debug("%s: gpio id %d idx %d happens\n",
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__func__, bank->id, idx);
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generic_handle_irq(irq_find_mapping(gc->irqdomain, idx +
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generic_handle_irq(irq_find_mapping(gc->irq.domain, idx +
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bank->id * SIRFSOC_GPIO_BANK_SIZE));
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}
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@ -401,7 +401,7 @@ static void plgpio_irq_handler(struct irq_desc *desc)
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/* get correct irq line number */
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pin = i * MAX_GPIO_PER_REG + pin;
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generic_handle_irq(
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irq_find_mapping(gc->irqdomain, pin));
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irq_find_mapping(gc->irq.domain, pin));
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}
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}
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chained_irq_exit(irqchip, desc);
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