From d0be758c9154e1223d04b3b7d24829bfedf40c07 Mon Sep 17 00:00:00 2001 From: David Dai Date: Wed, 28 Aug 2019 21:41:07 -0700 Subject: [PATCH] clk: qcom: clk-rcg2: add callbacks to deal with voltage voting Specify prepare, unprepare and pre/post rate change callbacks for all clk-rcg2 clk_ops. This ensures that supply regulator requirements are managed properly at runtime. Change-Id: I6d7e31983e99c2ef9f546771d7046e8f0111debc Signed-off-by: David Dai --- drivers/clk/qcom/clk-rcg2.c | 40 +++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 0c9cc046fac2..a19cae9e2c1d 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -629,6 +629,10 @@ static void clk_rcg2_disable(struct clk_hw *hw) } const struct clk_ops clk_rcg2_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .is_enabled = clk_rcg2_is_enabled, .enable = clk_rcg2_enable, .disable = clk_rcg2_disable, @@ -642,6 +646,10 @@ const struct clk_ops clk_rcg2_ops = { EXPORT_SYMBOL_GPL(clk_rcg2_ops); const struct clk_ops clk_rcg2_floor_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .is_enabled = clk_rcg2_is_enabled, .get_parent = clk_rcg2_get_parent, .set_parent = clk_rcg2_set_parent, @@ -771,6 +779,10 @@ static int clk_edp_pixel_determine_rate(struct clk_hw *hw, } const struct clk_ops clk_edp_pixel_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .is_enabled = clk_rcg2_is_enabled, .get_parent = clk_rcg2_get_parent, .set_parent = clk_rcg2_set_parent, @@ -831,6 +843,10 @@ static int clk_byte_set_rate_and_parent(struct clk_hw *hw, } const struct clk_ops clk_byte_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .is_enabled = clk_rcg2_is_enabled, .get_parent = clk_rcg2_get_parent, .set_parent = clk_rcg2_set_parent, @@ -901,6 +917,10 @@ static int clk_byte2_set_rate_and_parent(struct clk_hw *hw, } const struct clk_ops clk_byte2_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .is_enabled = clk_rcg2_is_enabled, .get_parent = clk_rcg2_get_parent, .set_parent = clk_rcg2_set_parent, @@ -991,6 +1011,10 @@ static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, } const struct clk_ops clk_pixel_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .is_enabled = clk_rcg2_is_enabled, .get_parent = clk_rcg2_get_parent, .set_parent = clk_rcg2_set_parent, @@ -1073,6 +1097,10 @@ static int clk_dp_determine_rate(struct clk_hw *hw, } const struct clk_ops clk_dp_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .is_enabled = clk_rcg2_is_enabled, .get_parent = clk_rcg2_get_parent, .set_parent = clk_rcg2_set_parent, @@ -1164,6 +1192,10 @@ static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate, } const struct clk_ops clk_gfx3d_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .is_enabled = clk_rcg2_is_enabled, .get_parent = clk_rcg2_get_parent, .set_parent = clk_rcg2_set_parent, @@ -1270,6 +1302,10 @@ static void clk_rcg2_shared_disable(struct clk_hw *hw) } const struct clk_ops clk_rcg2_shared_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .enable = clk_rcg2_shared_enable, .disable = clk_rcg2_shared_disable, .get_parent = clk_rcg2_get_parent, @@ -1414,6 +1450,10 @@ clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) } static const struct clk_ops clk_rcg2_dfs_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .is_enabled = clk_rcg2_is_enabled, .get_parent = clk_rcg2_get_parent, .determine_rate = clk_rcg2_dfs_determine_rate,