From 15e6d83b4b46b468a82c5fd8ddb0974b03193af6 Mon Sep 17 00:00:00 2001 From: Jack Pham Date: Thu, 21 May 2020 11:55:58 -0700 Subject: [PATCH] ARM: dts: msm: Update QMP Phy init sequence for Lahaina to v1.09 Update the QMP USB combo PHY init sequence to the HSR v1.09 updates. Change-Id: Ic0945f65fc036b6c9e1aee7a8bf870c04409e227 --- qcom/lahaina-usb.dtsi | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index 9b8a4930af5b..8725ad7e8f33 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -222,6 +222,7 @@ USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0 USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0E 0 USB3_DP_QSERDES_TXA_LANE_MODE_1 0x35 0 + USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F 0 USB3_DP_QSERDES_TXA_LANE_MODE_4 0x7F 0 USB3_DP_QSERDES_TXA_LANE_MODE_5 0x3F 0 USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0 @@ -252,8 +253,8 @@ USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xBB 0 USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3D 0 USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB 0 - USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x5B 0 - USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x1B 0 + USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x64 0 + USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x24 0 USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xD2 0 USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x13 0 USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xA9 0 @@ -268,6 +269,7 @@ USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0 USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0E 0 USB3_DP_QSERDES_TXB_LANE_MODE_1 0x35 0 + USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F 0 USB3_DP_QSERDES_TXB_LANE_MODE_4 0x7F 0 USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F 0 USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0 @@ -298,8 +300,8 @@ USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBB 0 USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3C 0 USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB 0 - USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x5B 0 - USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x1B 0 + USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x64 0 + USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x24 0 USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xD2 0 USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x13 0 USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xA9 0 @@ -308,6 +310,10 @@ USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0 USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0 USB3_DP_QSERDES_RXB_GM_CAL 0x00 0 + USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40 0 + USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00 0 + USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0 + USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0 USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0 USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0 0 USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0