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Merge "iommu/arm-smmu: Update the implementation defined page number macros"

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This commit is contained in:
qctecmdr 2020-12-10 11:38:50 -08:00 • committed by Gerrit - the friendly Code Review server
commit f16a9db54f
2 changed files with 20 additions and 14 deletions
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22
drivers/iommu/arm-smmu-qcom.c
View file

@ -19,9 +19,7 @@
#include <linux/debugfs.h>
#include <linux/uaccess.h>
#define ARM_SMMU_IMPL_DEF1 6
#define IMPL_DEF1_MICRO_MMU_CTRL 0
#define IMPL_DEF4_MICRO_MMU_CTRL 0
#define MICRO_MMU_CTRL_LOCAL_HALT_REQ BIT(2)
#define MICRO_MMU_CTRL_IDLE BIT(3)
@ -47,11 +45,11 @@ struct qsmmuv2_archdata {
static int qsmmuv2_wait_for_halt(struct arm_smmu_device *smmu)
{
void __iomem *reg = arm_smmu_page(smmu, ARM_SMMU_IMPL_DEF1);
void __iomem *reg = arm_smmu_page(smmu, ARM_SMMU_IMPL_DEF4);
struct device *dev = smmu->dev;
u32 tmp;
if (readl_poll_timeout_atomic(reg + IMPL_DEF1_MICRO_MMU_CTRL, tmp,
if (readl_poll_timeout_atomic(reg + IMPL_DEF4_MICRO_MMU_CTRL, tmp,
(tmp & MICRO_MMU_CTRL_IDLE), 0, 30000)) {
dev_err(dev, "Couldn't halt SMMU!\n");
return -EBUSY;
@ -64,11 +62,11 @@ static int __qsmmuv2_halt(struct arm_smmu_device *smmu, bool wait)
{
u32 val;
val = arm_smmu_readl(smmu, ARM_SMMU_IMPL_DEF1,
IMPL_DEF1_MICRO_MMU_CTRL);
val = arm_smmu_readl(smmu, ARM_SMMU_IMPL_DEF4,
IMPL_DEF4_MICRO_MMU_CTRL);
val |= MICRO_MMU_CTRL_LOCAL_HALT_REQ;
arm_smmu_writel(smmu, ARM_SMMU_IMPL_DEF1, IMPL_DEF1_MICRO_MMU_CTRL,
arm_smmu_writel(smmu, ARM_SMMU_IMPL_DEF4, IMPL_DEF4_MICRO_MMU_CTRL,
val);
return wait ? qsmmuv2_wait_for_halt(smmu) : 0;
@ -88,11 +86,11 @@ static void qsmmuv2_resume(struct arm_smmu_device *smmu)
{
u32 val;
val = arm_smmu_readl(smmu, ARM_SMMU_IMPL_DEF1,
IMPL_DEF1_MICRO_MMU_CTRL);
val = arm_smmu_readl(smmu, ARM_SMMU_IMPL_DEF4,
IMPL_DEF4_MICRO_MMU_CTRL);
val &= ~MICRO_MMU_CTRL_LOCAL_HALT_REQ;
arm_smmu_writel(smmu, ARM_SMMU_IMPL_DEF1, IMPL_DEF1_MICRO_MMU_CTRL,
arm_smmu_writel(smmu, ARM_SMMU_IMPL_DEF4, IMPL_DEF4_MICRO_MMU_CTRL,
val);
}
@ -1170,7 +1168,7 @@ static void qsmmuv500_tlb_sync_timeout(struct arm_smmu_device *smmu)
"TLB sync timed out -- SMMU may be deadlocked\n");
sync_inv_ack = arm_smmu_readl(smmu,
ARM_SMMU_IMPL_DEF0,
ARM_SMMU_IMPL_DEF5,
ARM_SMMU_STATS_SYNC_INV_TBU_ACK);
ret = qcom_scm_io_readl((unsigned long)(smmu->phys_addr +
ARM_SMMU_TBU_PWR_STATUS), &tbu_pwr_status);

12
drivers/iommu/arm-smmu.h
View file

@ -243,8 +243,8 @@ enum arm_smmu_cbar_type {
#define TLBSTATUS_SACTIVE BIT(0)
#define ARM_SMMU_CB_ATS1PR 0x800
/* Implementation Defined Register Space 0 registers*/
/* Relative to IMPL_DEF_0 page */
/* Implementation Defined Register Space 5 registers */
/* Relative to IMPL_DEF5 page */
#define ARM_SMMU_STATS_SYNC_INV_TBU_ACK 0x5dc
#define TBU_SYNC_ACK GENMASK(25, 17)
#define TBU_SYNC_REQ BIT(16)
@ -558,7 +558,15 @@ static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page,
#define ARM_SMMU_GR0 0
#define ARM_SMMU_GR1 1
/*
* Implementation defined space starts after SMMU GR space, so IMPL_DEF page n
* is page n + 2 in the SMMU register space.
*/
#define ARM_SMMU_IMPL_DEF0 2
#define ARM_SMMU_IMPL_DEF4 6
#define ARM_SMMU_IMPL_DEF5 7
#define ARM_SMMU_CB(s, n) ((s)->numpage + (n))
#define arm_smmu_gr0_read(s, o) \