From f1984dceeb20c3d9f5dc476571202abab2815328 Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Wed, 3 Jun 2020 12:26:10 -0700 Subject: [PATCH] dwc3-msm: Add support to vote USB FORCE_MEM_CORE_ON USB FORCE_MEM_CORE_ON is need to set 1 with GCC_USB30_MASTER_CLK to retain USB controller CSR when system is into CXPC (i.e. using MX instead of CX). Without this bit set, USB controller CSR is not retain once coming out of CXPC. Add support to vote this as clock and tie with USB GDSC functionality. Change-Id: I25e65a2d06848ef84ec5fd2041db8c6a8d9a7b4e Signed-off-by: Mayank Rana --- drivers/usb/dwc3/dwc3-msm.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c index 03cc12943df9..a36880ce39ab 100644 --- a/drivers/usb/dwc3/dwc3-msm.c +++ b/drivers/usb/dwc3/dwc3-msm.c @@ -399,6 +399,7 @@ struct dwc3_msm { struct list_head req_complete_list; struct clk *xo_clk; struct clk *core_clk; + struct clk *core_csr_clk; long core_clk_rate; long core_clk_rate_hs; struct clk *iface_clk; @@ -2178,7 +2179,15 @@ static int dwc3_msm_config_gdsc(struct dwc3_msm *mdwc, int on) dev_err(mdwc->dev, "unable to enable usb3 gdsc\n"); return ret; } + + ret = clk_prepare_enable(mdwc->core_csr_clk); + if (ret) { + regulator_disable(mdwc->dwc3_gdsc); + dev_err(mdwc->dev, "unable to enable core_csr_clks\n"); + return ret; + } } else { + clk_disable_unprepare(mdwc->core_csr_clk); ret = regulator_disable(mdwc->dwc3_gdsc); if (ret) { dev_err(mdwc->dev, "unable to disable usb3 gdsc\n"); @@ -3435,6 +3444,10 @@ static int dwc3_msm_get_clk_gdsc(struct dwc3_msm *mdwc) return ret; } + mdwc->core_csr_clk = devm_clk_get(mdwc->dev, "core_csr_clk"); + if (IS_ERR(mdwc->core_csr_clk)) + mdwc->core_csr_clk = NULL; + mdwc->core_reset = devm_reset_control_get(mdwc->dev, "core_reset"); if (IS_ERR(mdwc->core_reset)) { dev_err(mdwc->dev, "failed to get core_reset\n");