From 35c2fef8bfc4470c2d1d16173905af64a75d59c0 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 27 Aug 2020 00:03:28 +0530 Subject: [PATCH] drivers: soc: qcom: update sct table for LLCC on Shima Update the LLCC SCT table for Shima for clients to request slices from system cache. - Added new entries for cpuss1 and cpu_hwt. - Changed the priority for modemhp_grow and display. - Change the alignment of the table column to look readable. Change-Id: I9289a9cc8a029d51429aeb44453e0620021daf75 Signed-off-by: Mukesh Ojha --- drivers/soc/qcom/llcc-shima.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/soc/qcom/llcc-shima.c b/drivers/soc/qcom/llcc-shima.c index bca66d2e4513..05e18af6cc5a 100644 --- a/drivers/soc/qcom/llcc-shima.c +++ b/drivers/soc/qcom/llcc-shima.c @@ -52,15 +52,17 @@ static struct llcc_slice_config shima_data[] = { SCT_ENTRY(LLCC_CPUSS, 1, 1536, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1), - SCT_ENTRY(LLCC_MDMHPGRW, 7, 512, 2, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), - SCT_ENTRY(LLCC_CMPT, 10, 1536, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), - SCT_ENTRY(LLCC_GPUHTW, 11, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), - SCT_ENTRY(LLCC_GPU, 12, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1, 0), - SCT_ENTRY(LLCC_MMUHWT, 13, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1), - SCT_ENTRY(LLCC_DISP, 16, 1536, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), - SCT_ENTRY(LLCC_MDMPNG, 21, 1536, 0, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), - SCT_ENTRY(LLCC_MDMVPE, 29, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), - SCT_ENTRY(LLCC_WRTCH, 31, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1), + SCT_ENTRY(LLCC_MDMHPGRW, 7, 512, 3, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), + SCT_ENTRY(LLCC_CMPT, 10, 1536, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), + SCT_ENTRY(LLCC_GPUHTW, 11, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), + SCT_ENTRY(LLCC_GPU, 12, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1, 0), + SCT_ENTRY(LLCC_MMUHWT, 13, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1), + SCT_ENTRY(LLCC_DISP, 16, 1536, 2, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), + SCT_ENTRY(LLCC_MDMPNG, 21, 1536, 0, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), + SCT_ENTRY(LLCC_MDMVPE, 29, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), + SCT_ENTRY(LLCC_WRTCH, 31, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1), + SCT_ENTRY(LLCC_CPUSS1, 3, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), + SCT_ENTRY(LLCC_CPUHWT, 5, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1), }; static int shima_qcom_llcc_probe(struct platform_device *pdev)