diff --git a/bindings/media/msm-npu-pwrlevels.txt b/bindings/media/msm-npu-pwrlevels.txt new file mode 100644 index 000000000000..9a8a014c95d8 --- /dev/null +++ b/bindings/media/msm-npu-pwrlevels.txt @@ -0,0 +1,164 @@ +Qualcomm Technologies, Inc. NPU powerlevels + +Powerlevels are defined in sets by qcom,npu-pwrlevels. Each powerlevel defines +a series of clock frequencies. These frequencies are for the corresponding +clocks in the clocks property of the msm_npu device. + +qcom,npu-pwrlevels bindings: + +Required Properties: +- #address-cells: Should be set to 1 +- #size-cells: Should be set to 0 +- compatible: Must be qcom,npu-pwrlevels +- initial-pwrlevel: NPU initial wakeup power level, this is the index of the + child node. + +qcom,npu-pwrlevel: This is a child node defining power levels. +qcom,npu-pwrlevels must contain at least one power level node. Each child node +has the following properties: + +Required Properties: +- reg: Index of the powerlevel (0 = lowest performance) +- clk-freq: List of clock frequencies (in Hz) of each clock for the current + powerlevel. List of clocks and order described in: + Documentation/devicetree/bindings/media/msm-npu.txt + +Example: + qcom,npu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,npu-pwrlevels"; + initial-pwrlevel = <4>; + qcom,npu-pwrlevel@0 { + reg = <0>; + clk-freq = <9600000 + 9600000 + 19200000 + 19200000 + 19200000 + 19200000 + 9600000 + 60000000 + 19200000 + 19200000 + 30000000 + 19200000 + 19200000 + 19200000 + 19200000 + 19200000 + 9600000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@1 { + reg = <1>; + clk-freq = <300000000 + 300000000 + 19200000 + 100000000 + 19200000 + 19200000 + 300000000 + 150000000 + 19200000 + 19200000 + 60000000 + 100000000 + 100000000 + 37500000 + 100000000 + 19200000 + 300000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@2 { + reg = <2>; + clk-freq = <350000000 + 350000000 + 19200000 + 150000000 + 19200000 + 19200000 + 350000000 + 200000000 + 37500000 + 19200000 + 120000000 + 150000000 + 150000000 + 75000000 + 150000000 + 19200000 + 350000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@3 { + reg = <3>; + clk-freq = <400000000 + 400000000 + 19200000 + 200000000 + 19200000 + 19200000 + 400000000 + 300000000 + 37500000 + 19200000 + 120000000 + 200000000 + 200000000 + 75000000 + 200000000 + 19200000 + 400000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@4 { + reg = <4>; + clk-freq = <600000000 + 600000000 + 19200000 + 300000000 + 19200000 + 19200000 + 600000000 + 403000000 + 75000000 + 19200000 + 240000000 + 300000000 + 300000000 + 150000000 + 300000000 + 19200000 + 600000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@5 { + reg = <5>; + clk-freq = <715000000 + 715000000 + 19200000 + 350000000 + 19200000 + 19200000 + 715000000 + 533000000 + 75000000 + 19200000 + 240000000 + 350000000 + 350000000 + 150000000 + 350000000 + 19200000 + 715000000 + 19200000 + 0>; + }; + }; diff --git a/bindings/media/msm-npu.txt b/bindings/media/msm-npu.txt new file mode 100644 index 000000000000..f009650f728a --- /dev/null +++ b/bindings/media/msm-npu.txt @@ -0,0 +1,228 @@ +* Qualcomm Technologies, Inc. MSM NPU + +NPU (Neural Network Processing Unit) applies neural network processing + +Required properties: +- compatible: Must be "qcom,msm-npu" +- reg: Specify offset and length of the device register sets. +- reg-names: Names corresponding to the defined register sets. + - "npu_base": npu base registers +- interrupts: Specify the npu interrupts. +- interrupt-names: should specify relevant names to each interrupts + property defined. +- cache-slice-names: A set of names that identify the usecase names of a + client that uses cache slice. These strings are used to look up the + cache slice entries by name +- cache-slices: The tuple has phandle to llcc device as the first argument + and the second argument is the usecase id of the client +- clocks: clocks required for the device. +- clock-names: names of clocks required for the device. +- vdd-supply: Phandle for vdd regulator device node +- vdd_'reg'-supply: Reference to the regulator that supplies the corresponding + 'reg' domain, e.g. vdd_cx-supply. +- qcom,proxy-reg-names: Names of the regulators that need to be turned on/off + during proxy voting/unvoting. +- qcom,vdd_'reg'-uV-uA: Voltage and current values for the 'reg' regulator, + e.g. qcom,vdd_cx-uV-uA. +- mboxes: Phandle array for mailbox controllers to be used for IPC +- mbox-names: names of each mailboxes +- #cooling-cells: Should be set to 2 +- qcom,npubw-dev: a phandle to a device representing bus bandwidth requirements + (see devbw.txt) +- qcom,npu-pwrlevels: Container for NPU power levels + (see msm-npu-pwrlevels.txt) +Example: + msm_npu: qcom,msm_npu@9800000 { + compatible = "qcom,msm-npu"; + status = "ok"; + reg = <0x9800000 0x800000>; + reg-names = "npu_base"; + interrupts = ; + iommus = <&apps_smmu 0x1461 0x0>, <&apps_smmu 0x2061 0x0>; + cache-slice-names = "npu"; + cache-slices = <&llcc 23>; + clocks = <&clock_npucc NPU_CC_CAL_DP_CLK>, + <&clock_npucc NPU_CC_CAL_DP_CLK_SRC>, + <&clock_npucc NPU_CC_XO_CLK>, + <&clock_npucc NPU_CC_ARMWIC_CORE_CLK>, + <&clock_npucc NPU_CC_BTO_CORE_CLK>, + <&clock_npucc NPU_CC_BWMON_CLK>, + <&clock_npucc NPU_CC_CAL_DP_CDC_CLK>, + <&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>, + <&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_APB_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_CLK_SRC>, + <&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>, + <&clock_npucc NPU_CC_NPU_CPC_CLK>, + <&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>, + <&clock_npucc NPU_CC_PERF_CNT_CLK>, + <&clock_npucc NPU_CC_QTIMER_CORE_CLK>, + <&clock_npucc NPU_CC_SLEEP_CLK>; + clock-names = "cal_dp_clk", + "cal_dp_clk_src", + "xo_clk", + "armwic_core_clk", + "bto_core_clk", + "bwmon_clk", + "cal_dp_cdc_clk", + "comp_noc_axi_clk", + "conf_noc_ahb_clk", + "npu_core_apb_clk", + "npu_core_atb_clk", + "npu_core_clk", + "npu_core_clk_src", + "npu_core_cti_clk", + "npu_cpc_clk", + "npu_cpc_timer_clk", + "perf_cnt_clk", + "qtimer_core_clk", + "sleep_clk"; + vdd-supply = <&npu_core_gdsc>; + vdd_cx-supply = <&pm8150l_s6_level>; + qcom,proxy-reg-names ="vdd", "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + mboxes = <&qmp_npu0 0>, <&qmp_npu1 0>; + mbox-names = "npu_low", "npu_high"; + #cooling-cells = <2>; + qcom,npubw-dev = <&npu_npu_ddr_bw>; + qcom,npu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,npu-pwrlevels"; + initial-pwrlevel = <4>; + qcom,npu-pwrlevel@0 { + reg = <0>; + clk-freq = <9600000 + 9600000 + 19200000 + 19200000 + 19200000 + 19200000 + 9600000 + 60000000 + 19200000 + 19200000 + 30000000 + 19200000 + 19200000 + 19200000 + 19200000 + 19200000 + 9600000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@1 { + reg = <1>; + clk-freq = <300000000 + 300000000 + 19200000 + 100000000 + 19200000 + 19200000 + 300000000 + 150000000 + 19200000 + 19200000 + 60000000 + 100000000 + 100000000 + 37500000 + 100000000 + 19200000 + 300000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@2 { + reg = <2>; + clk-freq = <350000000 + 350000000 + 19200000 + 150000000 + 19200000 + 19200000 + 350000000 + 200000000 + 37500000 + 19200000 + 120000000 + 150000000 + 150000000 + 75000000 + 150000000 + 19200000 + 350000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@3 { + reg = <3>; + clk-freq = <400000000 + 400000000 + 19200000 + 200000000 + 19200000 + 19200000 + 400000000 + 300000000 + 37500000 + 19200000 + 120000000 + 200000000 + 200000000 + 75000000 + 200000000 + 19200000 + 400000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@4 { + reg = <4>; + clk-freq = <600000000 + 600000000 + 19200000 + 300000000 + 19200000 + 19200000 + 600000000 + 403000000 + 75000000 + 19200000 + 240000000 + 300000000 + 300000000 + 150000000 + 300000000 + 19200000 + 600000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@5 { + reg = <5>; + clk-freq = <715000000 + 715000000 + 19200000 + 350000000 + 19200000 + 19200000 + 715000000 + 533000000 + 75000000 + 19200000 + 240000000 + 350000000 + 350000000 + 150000000 + 350000000 + 19200000 + 715000000 + 19200000 + 0>; + }; + }; + }; diff --git a/qcom/sdmshrike-v2.dtsi b/qcom/sdmshrike-v2.dtsi index 8390c82107c9..eaa848dd6882 100644 --- a/qcom/sdmshrike-v2.dtsi +++ b/qcom/sdmshrike-v2.dtsi @@ -171,3 +171,162 @@ iommus = <&apps_smmu 0x2304 0x60>; }; }; + +&msm_npu { + iommus = <&apps_smmu 0x1481 0x400>, <&apps_smmu 0x1081 0x400>; + qcom,npu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,npu-pwrlevels"; + initial-pwrlevel = <5>; + qcom,npu-pwrlevel@0 { + reg = <0>; + vreg = <1>; + clk-freq = <0 + 0 + 0 + 100000000 + 300000000 + 300000000 + 19200000 + 150000000 + 100000000 + 37500000 + 19200000 + 60000000 + 100000000 + 19200000 + 19200000 + 0 + 19200000 + 300000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@1 { + reg = <1>; + vreg = <2>; + clk-freq = <0 + 0 + 0 + 150000000 + 400000000 + 400000000 + 37500000 + 200000000 + 150000000 + 75000000 + 19200000 + 120000000 + 150000000 + 19200000 + 19200000 + 0 + 19200000 + 400000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@2 { + reg = <2>; + vreg = <3>; + clk-freq = <0 + 0 + 0 + 200000000 + 487000000 + 487000000 + 37500000 + 300000000 + 200000000 + 150000000 + 19200000 + 240000000 + 200000000 + 19200000 + 19200000 + 0 + 19200000 + 487000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@3 { + reg = <3>; + vreg = <4>; + clk-freq = <0 + 0 + 0 + 300000000 + 652000000 + 652000000 + 75000000 + 403000000 + 300000000 + 150000000 + 19200000 + 240000000 + 300000000 + 19200000 + 19200000 + 0 + 19200000 + 652000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@4 { + reg = <4>; + vreg = <6>; + clk-freq = <0 + 0 + 0 + 400000000 + 811000000 + 811000000 + 75000000 + 533000000 + 400000000 + 150000000 + 19200000 + 300000000 + 400000000 + 19200000 + 19200000 + 0 + 19200000 + 811000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@5 { + reg = <5>; + vreg = <7>; + clk-freq = <0 + 0 + 0 + 400000000 + 908000000 + 908000000 + 75000000 + 533000000 + 400000000 + 150000000 + 19200000 + 300000000 + 400000000 + 19200000 + 19200000 + 0 + 19200000 + 908000000 + 19200000 + 19200000>; + }; + }; +}; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 6e7b1c5ec1a5..da8593875777 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -2090,6 +2090,7 @@ #include "sdmshrike-gpu.dtsi" #include "sa8195-vidc.dtsi" #include "sa8155-audio.dtsi" +#include "sm8150-npu.dtsi" #include "display/sdmshrike-sde-pll.dtsi" #include "display/sdmshrike-sde.dtsi" diff --git a/qcom/sm8150-npu.dtsi b/qcom/sm8150-npu.dtsi new file mode 100644 index 000000000000..06bda61d35d8 --- /dev/null +++ b/qcom/sm8150-npu.dtsi @@ -0,0 +1,192 @@ +&soc { + msm_npu: qcom,msm_npu@9800000 { + compatible = "qcom,msm-npu"; + status = "ok"; + reg = <0x9800000 0x40000>, + <0x9900000 0x10000>, + <0x9960200 0x600>; + reg-names = "tcm", "core", "bwmon"; + interrupts = , + , + ; + interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq"; + iommus = <&apps_smmu 0x1461 0x0>, <&apps_smmu 0x2061 0x0>; + clocks = <&aopcc QDSS_CLK>, + <&gcc GCC_NPU_AT_CLK>, + <&gcc GCC_NPU_TRIG_CLK>, + <&npucc NPU_CC_ARMWIC_CORE_CLK>, + <&npucc NPU_CC_CAL_DP_CLK>, + <&npucc NPU_CC_CAL_DP_CDC_CLK>, + <&npucc NPU_CC_CONF_NOC_AHB_CLK>, + <&npucc NPU_CC_COMP_NOC_AXI_CLK>, + <&npucc NPU_CC_NPU_CORE_CLK>, + <&npucc NPU_CC_NPU_CORE_CTI_CLK>, + <&npucc NPU_CC_NPU_CORE_APB_CLK>, + <&npucc NPU_CC_NPU_CORE_ATB_CLK>, + <&npucc NPU_CC_NPU_CPC_CLK>, + <&npucc NPU_CC_NPU_CPC_TIMER_CLK>, + <&npucc NPU_CC_QTIMER_CORE_CLK>, + <&npucc NPU_CC_SLEEP_CLK>, + <&npucc NPU_CC_BWMON_CLK>, + <&npucc NPU_CC_PERF_CNT_CLK>, + <&npucc NPU_CC_BTO_CORE_CLK>, + <&npucc NPU_CC_XO_CLK>; + clock-names = "qdss_clk", + "at_clk", + "trig_clk", + "armwic_core_clk", + "cal_dp_clk", + "cal_dp_cdc_clk", + "conf_noc_ahb_clk", + "comp_noc_axi_clk", + "npu_core_clk", + "npu_core_cti_clk", + "npu_core_apb_clk", + "npu_core_atb_clk", + "npu_cpc_clk", + "npu_cpc_timer_clk", + "qtimer_core_clk", + "sleep_clk", + "bwmon_clk", + "perf_cnt_clk", + "bto_core_clk", + "xo_clk"; + vdd-supply = <&npu_core_gdsc>; + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names ="vdd", "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + #cooling-cells = <2>; + qcom,npu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,npu-pwrlevels"; + initial-pwrlevel = <4>; + qcom,npu-pwrlevel@0 { + reg = <0>; + vreg = <1>; + clk-freq = <0 + 0 + 0 + 100000000 + 300000000 + 300000000 + 19200000 + 150000000 + 100000000 + 37500000 + 19200000 + 60000000 + 100000000 + 19200000 + 19200000 + 0 + 19200000 + 300000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@1 { + reg = <1>; + vreg = <2>; + clk-freq = <0 + 0 + 0 + 150000000 + 350000000 + 350000000 + 37500000 + 200000000 + 150000000 + 75000000 + 19200000 + 120000000 + 150000000 + 19200000 + 19200000 + 0 + 19200000 + 350000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@2 { + reg = <2>; + vreg = <3>; + clk-freq = <0 + 0 + 0 + 200000000 + 400000000 + 400000000 + 37500000 + 300000000 + 200000000 + 75000000 + 19200000 + 120000000 + 200000000 + 19200000 + 19200000 + 0 + 19200000 + 400000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@3 { + reg = <3>; + vreg = <4>; + clk-freq = <0 + 0 + 0 + 300000000 + 600000000 + 600000000 + 75000000 + 403000000 + 300000000 + 150000000 + 19200000 + 240000000 + 300000000 + 19200000 + 19200000 + 0 + 19200000 + 600000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@4 { + reg = <4>; + vreg = <6>; + clk-freq = <0 + 0 + 0 + 350000000 + 715000000 + 715000000 + 75000000 + 533000000 + 350000000 + 150000000 + 19200000 + 240000000 + 350000000 + 19200000 + 19200000 + 0 + 19200000 + 715000000 + 19200000 + 19200000>; + }; + }; + }; +}; diff --git a/qcom/sm8150-v2.dtsi b/qcom/sm8150-v2.dtsi index 6ab80cc54442..89f7cf5c1bfc 100644 --- a/qcom/sm8150-v2.dtsi +++ b/qcom/sm8150-v2.dtsi @@ -560,4 +560,165 @@ iommus = <&apps_smmu 0x2304 0x60>; }; }; + +/* NPU overrides */ +&msm_npu { + iommus = <&apps_smmu 0x1081 0x400>; + qcom,npu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,npu-pwrlevels"; + initial-pwrlevel = <5>; + qcom,npu-pwrlevel@0 { + reg = <0>; + vreg = <1>; + clk-freq = <0 + 0 + 0 + 100000000 + 300000000 + 300000000 + 19200000 + 150000000 + 100000000 + 37500000 + 19200000 + 60000000 + 100000000 + 19200000 + 19200000 + 0 + 19200000 + 300000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@1 { + reg = <1>; + vreg = <2>; + clk-freq = <0 + 0 + 0 + 150000000 + 400000000 + 400000000 + 37500000 + 200000000 + 150000000 + 75000000 + 19200000 + 120000000 + 150000000 + 19200000 + 19200000 + 0 + 19200000 + 400000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@2 { + reg = <2>; + vreg = <3>; + clk-freq = <0 + 0 + 0 + 200000000 + 487000000 + 487000000 + 37500000 + 300000000 + 200000000 + 150000000 + 19200000 + 240000000 + 200000000 + 19200000 + 19200000 + 0 + 19200000 + 487000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@3 { + reg = <3>; + vreg = <4>; + clk-freq = <0 + 0 + 0 + 300000000 + 652000000 + 652000000 + 75000000 + 403000000 + 300000000 + 150000000 + 19200000 + 240000000 + 300000000 + 19200000 + 19200000 + 0 + 19200000 + 652000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@4 { + reg = <4>; + vreg = <6>; + clk-freq = <0 + 0 + 0 + 400000000 + 811000000 + 811000000 + 75000000 + 533000000 + 400000000 + 150000000 + 19200000 + 300000000 + 400000000 + 19200000 + 19200000 + 0 + 19200000 + 811000000 + 19200000 + 19200000>; + }; + + qcom,npu-pwrlevel@5 { + reg = <5>; + vreg = <7>; + clk-freq = <0 + 0 + 0 + 400000000 + 908000000 + 908000000 + 75000000 + 533000000 + 400000000 + 150000000 + 19200000 + 300000000 + 400000000 + 19200000 + 19200000 + 0 + 19200000 + 908000000 + 19200000 + 19200000>; + }; + }; +}; + #include "camera/sm8150-v2-camera.dtsi" diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 2b998b1e9732..918fe64b6d84 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -2795,3 +2795,4 @@ #include "sm8150-pcie.dtsi" #include "sm8150-usb.dtsi" #include "sm8150-gpu.dtsi" +#include "sm8150-npu.dtsi"