From f201ff7cb5be1282e6effc7dcf98a3f7e16200db Mon Sep 17 00:00:00 2001
From: Ashok Vuyyuru <avuyyuru@qti.qualcomm.com>
Date: Thu, 26 May 2022 12:45:34 +0530
Subject: [PATCH] ARM: dts: msm: Updating right DDR AB/IB voting values

With current AB/IB values not meeting expected tput in concurrent
scenario. Adding changes to use right AB/IB votes for DDR to meet
tput requirements.

Change-Id: I21f02c5ae5e793d54e5669cfe375fb5b391721b2
---
 qcom/sdxlemur.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi
index bdde1284b724..82def0a0d2e1 100644
--- a/qcom/sdxlemur.dtsi
+++ b/qcom/sdxlemur.dtsi
@@ -1229,19 +1229,19 @@
 
 		/* SVS2 */
 		qcom,svs2 =
-		<50000 0 600000 1900000 0 76800>;
+		<780000  0 1300000 1800000 0 76800>;
 
 		/* SVS */
 		qcom,svs =
-		<490000 0 1200000 2800000 0 150000>;
+		<1290000 0 2160000 3000000 0 150000>;
 
 		/* NOMINAL */
 		qcom,nominal =
-		<800000 0 2400000 5500000 0 400000>;
+		<2820000 0 4300000 6000000 0 400000>;
 
 		/* TURBO */
 		qcom,turbo =
-		<1600000 0 3600000 5500000 0 400000>;
+		<3480000 0 6900000 9600000 0 400000>;
 
 		qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
 		"TURBO";