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cxl: Add psl9 specific code
The new Coherent Accelerator Interface Architecture, level 2, for the
IBM POWER9 brings new content and features:
- POWER9 Service Layer
- Registers
- Radix mode
- Process element entry
- Dedicated-Shared Process Programming Model
- Translation Fault Handling
- CAPP
- Memory Context ID
If a valid mm_struct is found the memory context id is used for each
transaction associated with the process handle. The PSL uses the
context ID to find the corresponding process element.
Signed-off-by: Christophe Lombard <[email protected]>
Acked-by: Frederic Barrat <[email protected]>
[mpe: Fixup comment formatting, unsplit long strings]
Signed-off-by: Michael Ellerman <[email protected]>
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@ -21,7 +21,7 @@ Introduction
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Hardware overview
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=================
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POWER8 FPGA
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POWER8/9 FPGA
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+----------+ +---------+
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| | | |
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| CPU | | AFU |
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@ -34,7 +34,7 @@ Hardware overview
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| | CAPP |<------>| |
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+---+------+ PCIE +---------+
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The POWER8 chip has a Coherently Attached Processor Proxy (CAPP)
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The POWER8/9 chip has a Coherently Attached Processor Proxy (CAPP)
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unit which is part of the PCIe Host Bridge (PHB). This is managed
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by Linux by calls into OPAL. Linux doesn't directly program the
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CAPP.
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@ -59,6 +59,17 @@ Hardware overview
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the fault. The context to which this fault is serviced is based on
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who owns that acceleration function.
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POWER8 <-----> PSL Version 8 is compliant to the CAIA Version 1.0.
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POWER9 <-----> PSL Version 9 is compliant to the CAIA Version 2.0.
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This PSL Version 9 provides new features such as:
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* Interaction with the nest MMU on the P9 chip.
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* Native DMA support.
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* Supports sending ASB_Notify messages for host thread wakeup.
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* Supports Atomic operations.
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* ....
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Cards with a PSL9 won't work on a POWER8 system and cards with a
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PSL8 won't work on a POWER9 system.
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AFU Modes
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=========
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