From f2d281367de0df4d4ffd7aecc59e8aee25cfbb32 Mon Sep 17 00:00:00 2001
From: Yuanfang Zhang <yuanfang@qti.qualcomm.com>
Date: Thu, 9 Jul 2020 18:39:37 +0800
Subject: [PATCH] ARM: dts: msm: add dcc node on sdxlemur

Add dcc node to enable dcc function on sdxlemur.

Change-Id: I4d140183e1958bd2f3eca2504c3017d5ffac9f84
---
 qcom/sdxlemur.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi
index 59ccc782eda4..caee7acf8b95 100644
--- a/qcom/sdxlemur.dtsi
+++ b/qcom/sdxlemur.dtsi
@@ -2,6 +2,7 @@
 #include <dt-bindings/clock/qcom,apsscc-sdxlemur.h>
 #include <dt-bindings/clock/qcom,gcc-sdxlemur.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/soc/qcom,dcc_v2.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interconnect/qcom,sdxlemur.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -190,6 +191,17 @@
 		reg-names = "pshold-base", "tcsr-boot-misc-detect";
 	};
 
+	dcc: dcc_v2@117f000 {
+		compatible = "qcom,dcc-v2";
+		reg = <0x117f000 0x1000>,
+		      <0x1100000 0x2000>;
+
+		qcom,transaction_timeout = <0>;
+
+		reg-names = "dcc-base", "dcc-ram-base";
+		dcc-ram-offset = <0x800>;
+	};
+
 	watchdog: qcom,wdt@17817000 {
 		compatible = "qcom,msm-watchdog";
 		reg = <0x17817000 0x1000>;