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PM / devfreq: bimc-bwmon: Add support for version 4
The version 4 of the BIMC BWMON hardware now has provisions for counting bytes transferred at a high sampling rate. Modify the existing driver and governor algorithm to take advantage of that. Change-Id: I5080297aef7e310d5c1a19098c177ddecb729c25 Signed-off-by: Rohit Gupta <rohgup@codeaurora.org> [avajid@codeaurora.org: made minor styling changes] Signed-off-by: Amir Vajid <avajid@codeaurora.org>
This commit is contained in:
Rohit Gupta
Amir Vajid
parent
7236ae6387
commit
f30d9fbf4c
1 changed files with 245 additions and 22 deletions
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014-2015, 2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2014-2016, 2019, The Linux Foundation. All rights reserved.
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*/
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#define pr_fmt(fmt) "bimc-bwmon: " fmt
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@ -10,6 +10,7 @@
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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@ -32,10 +33,24 @@
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#define MON_MASK(m) ((m)->base + 0x298)
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#define MON_MATCH(m) ((m)->base + 0x29C)
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#define MON2_EN(m) ((m)->base + 0x2A0)
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#define MON2_CLEAR(m) ((m)->base + 0x2A4)
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#define MON2_SW(m) ((m)->base + 0x2A8)
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#define MON2_THRES_HI(m) ((m)->base + 0x2AC)
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#define MON2_THRES_MED(m) ((m)->base + 0x2B0)
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#define MON2_THRES_LO(m) ((m)->base + 0x2B4)
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#define MON2_ZONE_ACTIONS(m) ((m)->base + 0x2B8)
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#define MON2_ZONE_CNT_THRES(m) ((m)->base + 0x2BC)
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#define MON2_BYTE_CNT(m) ((m)->base + 0x2D0)
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#define MON2_WIN_TIMER(m) ((m)->base + 0x2D4)
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#define MON2_ZONE_CNT(m) ((m)->base + 0x2D8)
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#define MON2_ZONE_MAX(m, zone) ((m)->base + 0x2E0 + 0x4 * zone)
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struct bwmon_spec {
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bool wrap_on_thres;
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bool overflow;
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bool throt_adj;
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bool hw_sampling;
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};
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struct bwmon {
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@ -46,24 +61,37 @@ struct bwmon {
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const struct bwmon_spec *spec;
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struct device *dev;
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struct bw_hwmon hw;
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u32 hw_timer_hz;
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u32 throttle_adj;
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u32 sample_size_ms;
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u32 intr_status;
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};
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#define to_bwmon(ptr) container_of(ptr, struct bwmon, hw)
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#define has_hw_sampling(m) (m->spec->hw_sampling)
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#define ENABLE_MASK BIT(0)
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#define THROTTLE_MASK 0x1F
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#define THROTTLE_SHIFT 16
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#define INT_ENABLE_V1 0x1
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#define INT_STATUS_MASK 0x03
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#define INT_STATUS_MASK_HWS 0xF0
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static DEFINE_SPINLOCK(glb_lock);
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static void mon_enable(struct bwmon *m)
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{
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writel_relaxed((ENABLE_MASK | m->throttle_adj), MON_EN(m));
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if (has_hw_sampling(m))
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writel_relaxed((ENABLE_MASK | m->throttle_adj), MON2_EN(m));
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else
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writel_relaxed((ENABLE_MASK | m->throttle_adj), MON_EN(m));
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}
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static void mon_disable(struct bwmon *m)
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{
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writel_relaxed(m->throttle_adj, MON_EN(m));
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if (has_hw_sampling(m))
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writel_relaxed(m->throttle_adj, MON2_EN(m));
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else
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writel_relaxed(m->throttle_adj, MON_EN(m));
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/*
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* mon_disable() and mon_irq_clear(),
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* If latter goes first and count happen to trigger irq, we would
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@ -72,17 +100,46 @@ static void mon_disable(struct bwmon *m)
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mb();
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}
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static void mon_clear(struct bwmon *m)
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#define MON_CLEAR_BIT 0x1
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#define MON_CLEAR_ALL_BIT 0x2
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static void mon_clear(struct bwmon *m, bool clear_all)
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{
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writel_relaxed(0x1, MON_CLEAR(m));
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if (!has_hw_sampling(m)) {
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writel_relaxed(MON_CLEAR_BIT, MON_CLEAR(m));
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goto out;
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}
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if (clear_all)
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writel_relaxed(MON_CLEAR_ALL_BIT, MON2_CLEAR(m));
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else
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writel_relaxed(MON_CLEAR_BIT, MON2_CLEAR(m));
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/*
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* The counter clear and IRQ clear bits are not in the same 4KB
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* region. So, we need to make sure the counter clear is completed
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* before we try to clear the IRQ or do any other counter operations.
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*/
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out:
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mb();
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}
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#define SAMPLE_WIN_LIM 0xFFFFF
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static void mon_set_hw_sampling_window(struct bwmon *m, unsigned int sample_ms)
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{
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u32 rate;
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if (unlikely(sample_ms != m->sample_size_ms)) {
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rate = mult_frac(sample_ms, m->hw_timer_hz, MSEC_PER_SEC);
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m->sample_size_ms = sample_ms;
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if (unlikely(rate > SAMPLE_WIN_LIM)) {
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rate = SAMPLE_WIN_LIM;
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pr_warn("Sample window %u larger than hw limit: %u\n",
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rate, SAMPLE_WIN_LIM);
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}
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writel_relaxed(rate, MON2_SW(m));
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}
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}
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static void mon_irq_enable(struct bwmon *m)
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{
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u32 val;
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@ -91,11 +148,11 @@ static void mon_irq_enable(struct bwmon *m)
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val = readl_relaxed(GLB_INT_EN(m));
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val |= 1 << m->mport;
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writel_relaxed(val, GLB_INT_EN(m));
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spin_unlock(&glb_lock);
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val = readl_relaxed(MON_INT_EN(m));
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val |= 0x1;
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val |= has_hw_sampling(m) ? INT_STATUS_MASK_HWS : INT_ENABLE_V1;
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writel_relaxed(val, MON_INT_EN(m));
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spin_unlock(&glb_lock);
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/*
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* make Sure irq enable complete for local and global
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* to avoid race with other monitor calls
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@ -111,11 +168,11 @@ static void mon_irq_disable(struct bwmon *m)
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val = readl_relaxed(GLB_INT_EN(m));
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val &= ~(1 << m->mport);
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writel_relaxed(val, GLB_INT_EN(m));
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spin_unlock(&glb_lock);
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val = readl_relaxed(MON_INT_EN(m));
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val &= ~0x1;
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val &= has_hw_sampling(m) ? ~INT_STATUS_MASK_HWS : ~INT_ENABLE_V1;
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writel_relaxed(val, MON_INT_EN(m));
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spin_unlock(&glb_lock);
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/*
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* make Sure irq disable complete for local and global
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* to avoid race with other monitor calls
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@ -132,12 +189,18 @@ static unsigned int mon_irq_status(struct bwmon *m)
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dev_dbg(m->dev, "IRQ status p:%x, g:%x\n", mval,
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readl_relaxed(GLB_INT_STATUS(m)));
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mval &= has_hw_sampling(m) ? INT_STATUS_MASK_HWS : INT_STATUS_MASK;
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return mval;
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}
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static void mon_irq_clear(struct bwmon *m)
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{
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writel_relaxed(0x3, MON_INT_CLR(m));
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u32 intclr;
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intclr = has_hw_sampling(m) ? INT_STATUS_MASK_HWS : INT_STATUS_MASK;
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writel_relaxed(intclr, MON_INT_CLR(m));
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/* Ensure the monitor IRQ is clear before clearing GLB IRQ */
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mb();
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writel_relaxed(1 << m->mport, GLB_INT_CLR(m));
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@ -165,6 +228,90 @@ static u32 mon_get_throttle_adj(struct bw_hwmon *hw)
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return m->throttle_adj >> THROTTLE_SHIFT;
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}
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#define ZONE1_SHIFT 8
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#define ZONE2_SHIFT 16
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#define ZONE3_SHIFT 24
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#define ZONE0_ACTION 0x01 /* Increment zone 0 count */
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#define ZONE1_ACTION 0x09 /* Increment zone 1 & clear lower zones */
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#define ZONE2_ACTION 0x25 /* Increment zone 2 & clear lower zones */
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#define ZONE3_ACTION 0x95 /* Increment zone 3 & clear lower zones */
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static u32 calc_zone_actions(void)
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{
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u32 zone_actions;
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zone_actions = ZONE0_ACTION;
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zone_actions |= ZONE1_ACTION << ZONE1_SHIFT;
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zone_actions |= ZONE2_ACTION << ZONE2_SHIFT;
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zone_actions |= ZONE3_ACTION << ZONE3_SHIFT;
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return zone_actions;
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}
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#define ZONE_CNT_LIM 0xFFU
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#define UP_CNT_1 1
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static u32 calc_zone_counts(struct bw_hwmon *hw)
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{
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u32 zone_counts;
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zone_counts = ZONE_CNT_LIM;
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zone_counts |= min(hw->down_cnt, ZONE_CNT_LIM) << ZONE1_SHIFT;
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zone_counts |= ZONE_CNT_LIM << ZONE2_SHIFT;
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zone_counts |= UP_CNT_1 << ZONE3_SHIFT;
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return zone_counts;
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}
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static unsigned int mbps_to_mb(unsigned long mbps, unsigned int ms)
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{
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mbps *= ms;
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mbps = DIV_ROUND_UP(mbps, MSEC_PER_SEC);
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return mbps;
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}
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/*
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* Define the 4 zones using HI, MED & LO thresholds:
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* Zone 0: byte count < THRES_LO
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* Zone 1: THRES_LO < byte count < THRES_MED
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* Zone 2: THRES_MED < byte count < THRES_HI
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* Zone 3: byte count > THRES_HI
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*/
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#define THRES_LIM 0x7FFU
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static void set_zone_thres(struct bwmon *m, unsigned int sample_ms)
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{
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struct bw_hwmon *hw = &(m->hw);
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u32 hi, med, lo;
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hi = mbps_to_mb(hw->up_wake_mbps, sample_ms);
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med = mbps_to_mb(hw->down_wake_mbps, sample_ms);
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lo = 0;
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if (unlikely((hi > THRES_LIM) || (med > hi) || (lo > med))) {
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pr_warn("Zone thres larger than hw limit: hi:%u med:%u lo:%u\n",
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hi, med, lo);
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hi = min(hi, THRES_LIM);
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med = min(med, hi - 1);
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lo = min(lo, med-1);
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}
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writel_relaxed(hi, MON2_THRES_HI(m));
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writel_relaxed(med, MON2_THRES_MED(m));
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writel_relaxed(lo, MON2_THRES_LO(m));
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dev_dbg(m->dev, "Thres: hi:%u med:%u lo:%u\n", hi, med, lo);
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}
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static void mon_set_zones(struct bwmon *m, unsigned int sample_ms)
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{
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struct bw_hwmon *hw = &(m->hw);
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u32 zone_cnt_thres = calc_zone_counts(hw);
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mon_set_hw_sampling_window(m, sample_ms);
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set_zone_thres(m, sample_ms);
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/* Set the zone count thresholds for interrupts */
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writel_relaxed(zone_cnt_thres, MON2_ZONE_CNT_THRES(m));
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dev_dbg(m->dev, "Zone Count Thres: %0x\n", zone_cnt_thres);
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}
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static void mon_set_limit(struct bwmon *m, u32 count)
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{
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writel_relaxed(count, MON_THRES(m));
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@ -197,6 +344,41 @@ static unsigned long mon_get_count(struct bwmon *m)
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return count;
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}
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static unsigned int get_zone(struct bwmon *m)
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{
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u32 zone_counts;
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u32 zone;
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zone = get_bitmask_order((m->intr_status & INT_STATUS_MASK_HWS) >> 4);
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if (zone) {
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zone--;
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} else {
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zone_counts = readl_relaxed(MON2_ZONE_CNT(m));
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if (zone_counts) {
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zone = get_bitmask_order(zone_counts) - 1;
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zone /= 8;
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}
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}
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m->intr_status = 0;
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return zone;
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}
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static unsigned long mon_get_zone_stats(struct bwmon *m)
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{
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unsigned int zone;
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unsigned long count = 0;
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zone = get_zone(m);
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count = readl_relaxed(MON2_ZONE_MAX(m, zone)) + 1;
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count *= SZ_1M;
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dev_dbg(m->dev, "Zone%d Max byte count: %08lx\n", zone, count);
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return count;
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}
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/* ********** CPUBW specific code ********** */
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/* Returns MBps of read/writes for the sampling window. */
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@ -216,8 +398,8 @@ static unsigned long get_bytes_and_clear(struct bw_hwmon *hw)
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unsigned long count;
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mon_disable(m);
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count = mon_get_count(m);
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mon_clear(m);
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count = has_hw_sampling(m) ? mon_get_zone_stats(m) : mon_get_count(m);
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mon_clear(m, false);
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mon_irq_clear(m);
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mon_enable(m);
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@ -232,7 +414,7 @@ static unsigned long set_thres(struct bw_hwmon *hw, unsigned long bytes)
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mon_disable(m);
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count = mon_get_count(m);
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mon_clear(m);
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mon_clear(m, false);
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mon_irq_clear(m);
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if (likely(!m->spec->wrap_on_thres))
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@ -246,11 +428,26 @@ static unsigned long set_thres(struct bw_hwmon *hw, unsigned long bytes)
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return count;
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}
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static unsigned long set_hw_events(struct bw_hwmon *hw, unsigned int sample_ms)
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{
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struct bwmon *m = to_bwmon(hw);
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mon_disable(m);
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mon_clear(m, false);
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mon_irq_clear(m);
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mon_set_zones(m, sample_ms);
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mon_enable(m);
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return 0;
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}
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static irqreturn_t bwmon_intr_handler(int irq, void *dev)
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{
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struct bwmon *m = dev;
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if (!mon_irq_status(m))
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m->intr_status = mon_irq_status(m);
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if (!m->intr_status)
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return IRQ_NONE;
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if (bw_hwmon_sample_end(&m->hw) > 0)
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@ -271,6 +468,7 @@ static int start_bw_hwmon(struct bw_hwmon *hw, unsigned long mbps)
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{
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struct bwmon *m = to_bwmon(hw);
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u32 limit;
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u32 zone_actions = calc_zone_actions();
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int ret;
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ret = request_threaded_irq(m->irq, bwmon_intr_handler,
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@ -285,10 +483,16 @@ static int start_bw_hwmon(struct bw_hwmon *hw, unsigned long mbps)
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mon_disable(m);
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mon_clear(m, true);
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limit = mbps_to_bytes(mbps, hw->df->profile->polling_ms, 0);
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mon_set_limit(m, limit);
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if (has_hw_sampling(m)) {
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mon_set_zones(m, hw->df->profile->polling_ms);
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/* Set the zone actions to increment appropriate counters */
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writel_relaxed(zone_actions, MON2_ZONE_ACTIONS(m));
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} else {
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mon_set_limit(m, limit);
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}
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mon_clear(m);
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mon_irq_clear(m);
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mon_irq_enable(m);
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mon_enable(m);
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@ -303,7 +507,7 @@ static void stop_bw_hwmon(struct bw_hwmon *hw)
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mon_irq_disable(m);
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free_irq(m->irq, m);
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mon_disable(m);
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mon_clear(m);
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mon_clear(m, true);
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mon_irq_clear(m);
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}
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@ -324,7 +528,7 @@ static int resume_bw_hwmon(struct bw_hwmon *hw)
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struct bwmon *m = to_bwmon(hw);
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int ret;
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mon_clear(m);
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mon_clear(m, false);
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ret = request_threaded_irq(m->irq, bwmon_intr_handler,
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bwmon_intr_thread,
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IRQF_ONESHOT | IRQF_SHARED,
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@ -344,15 +548,21 @@ static int resume_bw_hwmon(struct bw_hwmon *hw)
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/*************************************************************************/
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static const struct bwmon_spec spec[] = {
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{ .wrap_on_thres = true, .overflow = false, .throt_adj = false},
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{ .wrap_on_thres = false, .overflow = true, .throt_adj = false},
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{ .wrap_on_thres = false, .overflow = true, .throt_adj = true},
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{ .wrap_on_thres = true, .overflow = false, .throt_adj = false,
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.hw_sampling = false},
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{ .wrap_on_thres = false, .overflow = true, .throt_adj = false,
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.hw_sampling = false},
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{ .wrap_on_thres = false, .overflow = true, .throt_adj = true,
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.hw_sampling = false},
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{ .wrap_on_thres = false, .overflow = true, .throt_adj = true,
|
||||
.hw_sampling = true},
|
||||
};
|
||||
|
||||
static const struct of_device_id bimc_bwmon_match_table[] = {
|
||||
{ .compatible = "qcom,bimc-bwmon", .data = &spec[0] },
|
||||
{ .compatible = "qcom,bimc-bwmon2", .data = &spec[1] },
|
||||
{ .compatible = "qcom,bimc-bwmon3", .data = &spec[2] },
|
||||
{ .compatible = "qcom,bimc-bwmon4", .data = &spec[3] },
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
@ -384,6 +594,17 @@ static int bimc_bwmon_driver_probe(struct platform_device *pdev)
|
|||
}
|
||||
m->spec = id->data;
|
||||
|
||||
if (has_hw_sampling(m)) {
|
||||
ret = of_property_read_u32(dev->of_node,
|
||||
"qcom,hw-timer-hz", &data);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "HW sampling rate not specified! (%d)\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
m->hw_timer_hz = data;
|
||||
}
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
|
||||
if (!res) {
|
||||
dev_err(dev, "base not found!\n");
|
||||
|
|
@ -420,7 +641,9 @@ static int bimc_bwmon_driver_probe(struct platform_device *pdev)
|
|||
m->hw.suspend_hwmon = &suspend_bw_hwmon;
|
||||
m->hw.resume_hwmon = &resume_bw_hwmon;
|
||||
m->hw.get_bytes_and_clear = &get_bytes_and_clear;
|
||||
m->hw.set_thres = &set_thres;
|
||||
m->hw.set_thres = &set_thres;
|
||||
if (has_hw_sampling(m))
|
||||
m->hw.set_hw_events = &set_hw_events;
|
||||
if (m->spec->throt_adj) {
|
||||
m->hw.set_throttle_adj = &mon_set_throttle_adj;
|
||||
m->hw.get_throttle_adj = &mon_get_throttle_adj;
|
||||
|
|
|
|||
Loading…
Reference in a new issue