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dmaengine: PL08x: Fix reading the byte count in cctl

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There are more fields than just SWIDTH in CH_CONTROL register, so read
register value must be masked in addition to shifting.

Signed-off-by: Alban Bedel <[email protected]>
Signed-off-by: Tomasz Figa <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
This commit is contained in:
Alban Bedel 2013-08-11 19:59:19 +02:00 • committed by Vinod Koul
commit f3287a5206
1 changed files with 4 additions and 0 deletions
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4
drivers/dma/amba-pl08x.c
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@ -480,6 +480,8 @@ static inline u32 get_bytes_in_cctl(u32 cctl)
/* The source width defines the number of bytes */
u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
cctl &= PL080_CONTROL_SWIDTH_MASK;
switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
case PL080_WIDTH_8BIT:
break;
@ -498,6 +500,8 @@ static inline u32 get_bytes_in_cctl_pl080s(u32 cctl, u32 cctl1)
/* The source width defines the number of bytes */
u32 bytes = cctl1 & PL080S_CONTROL_TRANSFER_SIZE_MASK;
cctl &= PL080_CONTROL_SWIDTH_MASK;
switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
case PL080_WIDTH_8BIT:
break;