diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c
index 866b34962622..f6b0bf5f4383 100644
--- a/drivers/pci/controller/pci-msm.c
+++ b/drivers/pci/controller/pci-msm.c
@@ -864,9 +864,9 @@ static struct msm_pcie_clk_info_t
 	{NULL, "pcie_0_smmu_clk", 0, false, false},
 	{NULL, "pcie_0_slv_q2a_axi_clk", 0, false, false},
 	{NULL, "pcie_0_sleep_clk", 0, false, false},
-	{NULL, "pcie_phy_refgen_clk", 0, false, true},
-	{NULL, "pcie_tbu_clk", 0, false, true},
-	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},
+	{NULL, "pcie_phy_refgen_clk", 0, false, false},
+	{NULL, "pcie_tbu_clk", 0, false, false},
+	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},
 	{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},
 	{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},
 	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
@@ -884,9 +884,9 @@ static struct msm_pcie_clk_info_t
 	{NULL, "pcie_1_smmu_clk", 0, false, false},
 	{NULL, "pcie_1_slv_q2a_axi_clk", 0, false, false},
 	{NULL, "pcie_1_sleep_clk", 0, false, false},
-	{NULL, "pcie_phy_refgen_clk", 0, false, true},
-	{NULL, "pcie_tbu_clk", 0, false, true},
-	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},
+	{NULL, "pcie_phy_refgen_clk", 0, false, false},
+	{NULL, "pcie_tbu_clk", 0, false, false},
+	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},
 	{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},
 	{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},
 	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
@@ -904,9 +904,9 @@ static struct msm_pcie_clk_info_t
 	{NULL, "pcie_2_smmu_clk", 0, false, false},
 	{NULL, "pcie_2_slv_q2a_axi_clk", 0, false, false},
 	{NULL, "pcie_2_sleep_clk", 0, false, false},
-	{NULL, "pcie_phy_refgen_clk", 0, false, true},
-	{NULL, "pcie_tbu_clk", 0, false, true},
-	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},
+	{NULL, "pcie_phy_refgen_clk", 0, false, false},
+	{NULL, "pcie_tbu_clk", 0, false, false},
+	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},
 	{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},
 	{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},
 	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},