mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 11:41:38 -04:00
OpenRISC updates for v4.15
Small Things:
- Move OpenRISC docs into Documentation and clean them up
- Document previously undocumented devicetree bindings
- Update the or1ksim dts to use stdout-path
OpenRISC SMP support details:
- First the "use shadow registers" and "define CPU_BIG_ENDIAN as true"
get the architecture ready for SMP.
- The "add 1 and 2 byte cmpxchg support" and "use qspinlocks and
qrwlocks" add the SMP locking infrastructure as needed. Using the
qspinlocks and qrwlocks as suggested by Peter Z while reviewing the
original spinlocks implementation.
- The "support for ompic" adds a new irqchip device which is used for
IPI communication to support SMP.
- The "initial SMP support" adds smp.c and makes changes to all of the
necessary data-structures to be per-cpu.
- The remaining patches are bug fixes and debug helpers which I wanted
to keep separate from the "initial SMP support" in order to allow them
to be reviewed on their own. This includes:
- add cacheflush support to fix icache aliasing
- fix initial preempt state for secondary cpu tasks
- sleep instead of spin on secondary wait
- support framepointers and STACKTRACE_SUPPORT
- enable LOCKDEP_SUPPORT and irqflags tracing
- timer sync: Add tick timer sync logic
- fix possible deadlock in timer sync, pointed out by mips guys
Note: the irqchip patch was reviewed with Marc and we agreed to push it
together with these patches.
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Merge tag 'for-linus' of git://github.com/openrisc/linux
Pull OpenRISC updates from Stafford Horne:
"The OpenRISC work is a bit more interesting this time, adding SMP
support and a few general cleanups.
Small Things:
- Move OpenRISC docs into Documentation and clean them up
- Document previously undocumented devicetree bindings
- Update the or1ksim dts to use stdout-path
OpenRISC SMP support details:
- First the "use shadow registers" and "define CPU_BIG_ENDIAN as
true" get the architecture ready for SMP.
- The "add 1 and 2 byte cmpxchg support" and "use qspinlocks and
qrwlocks" add the SMP locking infrastructure as needed. Using the
qspinlocks and qrwlocks as suggested by Peter Z while reviewing the
original spinlocks implementation.
- The "support for ompic" adds a new irqchip device which is used for
IPI communication to support SMP.
- The "initial SMP support" adds smp.c and makes changes to all of
the necessary data-structures to be per-cpu.
The remaining patches are bug fixes and debug helpers which I wanted
to keep separate from the "initial SMP support" in order to allow them
to be reviewed on their own. This includes:
- add cacheflush support to fix icache aliasing
- fix initial preempt state for secondary cpu tasks
- sleep instead of spin on secondary wait
- support framepointers and STACKTRACE_SUPPORT
- enable LOCKDEP_SUPPORT and irqflags tracing
- timer sync: Add tick timer sync logic
- fix possible deadlock in timer sync, pointed out by mips guys
Note: the irqchip patch was reviewed with Marc and we agreed to push
it together with these patches"
* tag 'for-linus' of git://github.com/openrisc/linux:
openrisc: fix possible deadlock scenario during timer sync
openrisc: pass endianness info to sparse
openrisc: add tick timer multi-core sync logic
openrisc: enable LOCKDEP_SUPPORT and irqflags tracing
openrisc: support framepointers and STACKTRACE_SUPPORT
openrisc: add simple_smp dts and defconfig for simulators
openrisc: add cacheflush support to fix icache aliasing
openrisc: sleep instead of spin on secondary wait
openrisc: fix initial preempt state for secondary cpu tasks
openrisc: initial SMP support
irqchip: add initial support for ompic
dt-bindings: add openrisc to vendor prefixes list
openrisc: use qspinlocks and qrwlocks
openrisc: add 1 and 2 byte cmpxchg support
openrisc: use shadow registers to save regs on exception
dt-bindings: openrisc: Add OpenRISC platform SoC
Documentation: openrisc: Updates to README
Documentation: Move OpenRISC docs out of arch/
MAINTAINERS: Add OpenRISC pic maintainer
openrisc: dts: or1ksim: Add stdout-path
This commit is contained in:
Linus Torvalds
commit
f3573b8f90
46 changed files with 1940 additions and 262 deletions
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@ -151,6 +151,9 @@ config CLPS711X_IRQCHIP
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select SPARSE_IRQ
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default y
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config OMPIC
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bool
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config OR1K_PIC
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bool
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select IRQ_DOMAIN
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@ -18,6 +18,7 @@ obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
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obj-$(CONFIG_METAG) += irq-metag-ext.o
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obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
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obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
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obj-$(CONFIG_OMPIC) += irq-ompic.o
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obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o
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obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
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obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o
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202
drivers/irqchip/irq-ompic.c
Normal file
202
drivers/irqchip/irq-ompic.c
Normal file
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@ -0,0 +1,202 @@
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/*
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* Open Multi-Processor Interrupt Controller driver
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*
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* Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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* Copyright (C) 2017 Stafford Horne <shorne@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*
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* The ompic device handles IPI communication between cores in multi-core
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* OpenRISC systems.
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*
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* Registers
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*
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* For each CPU the ompic has 2 registers. The control register for sending
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* and acking IPIs and the status register for receiving IPIs. The register
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* layouts are as follows:
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*
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* Control register
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* +---------+---------+----------+---------+
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* | 31 | 30 | 29 .. 16 | 15 .. 0 |
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* ----------+---------+----------+----------
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* | IRQ ACK | IRQ GEN | DST CORE | DATA |
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* +---------+---------+----------+---------+
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*
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* Status register
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* +----------+-------------+----------+---------+
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* | 31 | 30 | 29 .. 16 | 15 .. 0 |
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* -----------+-------------+----------+---------+
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* | Reserved | IRQ Pending | SRC CORE | DATA |
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* +----------+-------------+----------+---------+
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*
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* Architecture
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*
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* - The ompic generates a level interrupt to the CPU PIC when a message is
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* ready. Messages are delivered via the memory bus.
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* - The ompic does not have any interrupt input lines.
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* - The ompic is wired to the same irq line on each core.
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* - Devices are wired to the same irq line on each core.
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*
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* +---------+ +---------+
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* | CPU | | CPU |
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* | Core 0 |<==\ (memory access) /==>| Core 1 |
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* | [ PIC ]| | | | [ PIC ]|
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* +----^-^--+ | | +----^-^--+
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* | | v v | |
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* <====|=|=================================|=|==> (memory bus)
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* | | ^ ^ | |
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* (ipi | +------|---------+--------|-------|-+ (device irq)
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* irq | | | | |
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* core0)| +------|---------|--------|-------+ (ipi irq core1)
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* | | | | |
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* +----o-o-+ | +--------+ |
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* | ompic |<===/ | Device |<===/
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* | IPI | +--------+
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* +--------+*
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*
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*/
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/irqchip.h>
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#define OMPIC_CPUBYTES 8
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#define OMPIC_CTRL(cpu) (0x0 + (cpu * OMPIC_CPUBYTES))
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#define OMPIC_STAT(cpu) (0x4 + (cpu * OMPIC_CPUBYTES))
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#define OMPIC_CTRL_IRQ_ACK (1 << 31)
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#define OMPIC_CTRL_IRQ_GEN (1 << 30)
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#define OMPIC_CTRL_DST(cpu) (((cpu) & 0x3fff) << 16)
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#define OMPIC_STAT_IRQ_PENDING (1 << 30)
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#define OMPIC_DATA(x) ((x) & 0xffff)
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DEFINE_PER_CPU(unsigned long, ops);
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static void __iomem *ompic_base;
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static inline u32 ompic_readreg(void __iomem *base, loff_t offset)
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{
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return ioread32be(base + offset);
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}
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static void ompic_writereg(void __iomem *base, loff_t offset, u32 data)
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{
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iowrite32be(data, base + offset);
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}
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static void ompic_raise_softirq(const struct cpumask *mask,
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unsigned int ipi_msg)
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{
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unsigned int dst_cpu;
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unsigned int src_cpu = smp_processor_id();
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for_each_cpu(dst_cpu, mask) {
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set_bit(ipi_msg, &per_cpu(ops, dst_cpu));
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/*
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* On OpenRISC the atomic set_bit() call implies a memory
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* barrier. Otherwise we would need: smp_wmb(); paired
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* with the read in ompic_ipi_handler.
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*/
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ompic_writereg(ompic_base, OMPIC_CTRL(src_cpu),
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OMPIC_CTRL_IRQ_GEN |
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OMPIC_CTRL_DST(dst_cpu) |
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OMPIC_DATA(1));
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}
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}
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static irqreturn_t ompic_ipi_handler(int irq, void *dev_id)
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{
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unsigned int cpu = smp_processor_id();
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unsigned long *pending_ops = &per_cpu(ops, cpu);
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unsigned long ops;
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ompic_writereg(ompic_base, OMPIC_CTRL(cpu), OMPIC_CTRL_IRQ_ACK);
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while ((ops = xchg(pending_ops, 0)) != 0) {
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/*
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* On OpenRISC the atomic xchg() call implies a memory
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* barrier. Otherwise we may need an smp_rmb(); paired
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* with the write in ompic_raise_softirq.
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*/
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do {
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unsigned long ipi_msg;
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ipi_msg = __ffs(ops);
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ops &= ~(1UL << ipi_msg);
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handle_IPI(ipi_msg);
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} while (ops);
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}
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return IRQ_HANDLED;
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}
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static int __init ompic_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct resource res;
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int irq;
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int ret;
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/* Validate the DT */
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if (ompic_base) {
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pr_err("ompic: duplicate ompic's are not supported");
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return -EEXIST;
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}
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if (of_address_to_resource(node, 0, &res)) {
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pr_err("ompic: reg property requires an address and size");
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return -EINVAL;
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}
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if (resource_size(&res) < (num_possible_cpus() * OMPIC_CPUBYTES)) {
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pr_err("ompic: reg size, currently %d must be at least %d",
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resource_size(&res),
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(num_possible_cpus() * OMPIC_CPUBYTES));
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return -EINVAL;
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}
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/* Setup the device */
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ompic_base = ioremap(res.start, resource_size(&res));
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if (IS_ERR(ompic_base)) {
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pr_err("ompic: unable to map registers");
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return PTR_ERR(ompic_base);
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}
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irq = irq_of_parse_and_map(node, 0);
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if (irq <= 0) {
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pr_err("ompic: unable to parse device irq");
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ret = -EINVAL;
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goto out_unmap;
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}
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ret = request_irq(irq, ompic_ipi_handler, IRQF_PERCPU,
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"ompic_ipi", NULL);
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if (ret)
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goto out_irq_disp;
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set_smp_cross_call(ompic_raise_softirq);
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return 0;
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out_irq_disp:
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irq_dispose_mapping(irq);
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out_unmap:
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iounmap(ompic_base);
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ompic_base = NULL;
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return ret;
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}
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IRQCHIP_DECLARE(ompic, "openrisc,ompic", ompic_of_init);
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