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Core changes:

Browse source 
- Parse the 4BAIT SFDP section
 - Add a bunch of SPI NOR entries to the flash_info table
 - Add the concept of SFDP fixups and use it to fix a bug on MX25L25635F
 - A bunch of minor cleanups/comestic changes
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Merge tag 'spi-nor/for-4.21' of git://git.infradead.org/linux-mtd into mtd/next

Core changes:
- Parse the 4BAIT SFDP section
- Add a bunch of SPI NOR entries to the flash_info table
- Add the concept of SFDP fixups and use it to fix a bug on MX25L25635F
- A bunch of minor cleanups/comestic changes
This commit is contained in:
Boris Brezillon 2018-12-18 20:00:52 +01:00
commit f366d3854e
786 changed files with 9765 additions and 5432 deletions
Download patch file Download diff file Expand all files Collapse all files

3
drivers/mtd/nand/bbt.c
View file

@ -27,7 +27,8 @@ int nanddev_bbt_init(struct nand_device *nand)
unsigned int nwords = DIV_ROUND_UP(nblocks * bits_per_block,
BITS_PER_LONG);
nand->bbt.cache = kzalloc(nwords, GFP_KERNEL);
nand->bbt.cache = kcalloc(nwords, sizeof(*nand->bbt.cache),
GFP_KERNEL);
if (!nand->bbt.cache)
return -ENOMEM;

11
drivers/mtd/nand/raw/atmel/nand-controller.c
View file

@ -2033,8 +2033,7 @@ atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
int ret;
nand_np = dev->of_node;
nfc_np = of_find_compatible_node(dev->of_node, NULL,
"atmel,sama5d3-nfc");
nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc");
if (!nfc_np) {
dev_err(dev, "Could not find device node for sama5d3-nfc\n");
return -ENODEV;
@ -2448,15 +2447,19 @@ static int atmel_nand_controller_probe(struct platform_device *pdev)
}
if (caps->legacy_of_bindings) {
struct device_node *nfc_node;
u32 ale_offs = 21;
/*
* If we are parsing legacy DT props and the DT contains a
* valid NFC node, forward the request to the sama5 logic.
*/
if (of_find_compatible_node(pdev->dev.of_node, NULL,
"atmel,sama5d3-nfc"))
nfc_node = of_get_compatible_child(pdev->dev.of_node,
"atmel,sama5d3-nfc");
if (nfc_node) {
caps = &atmel_sama5_nand_caps;
of_node_put(nfc_node);
}
/*
* Even if the compatible says we are dealing with an

32
drivers/mtd/nand/raw/qcom_nandc.c
View file

@ -150,15 +150,15 @@
#define NAND_VERSION_MINOR_SHIFT 16
/* NAND OP_CMDs */
#define PAGE_READ 0x2
#define PAGE_READ_WITH_ECC 0x3
#define PAGE_READ_WITH_ECC_SPARE 0x4
#define PROGRAM_PAGE 0x6
#define PAGE_PROGRAM_WITH_ECC 0x7
#define PROGRAM_PAGE_SPARE 0x9
#define BLOCK_ERASE 0xa
#define FETCH_ID 0xb
#define RESET_DEVICE 0xd
#define OP_PAGE_READ 0x2
#define OP_PAGE_READ_WITH_ECC 0x3
#define OP_PAGE_READ_WITH_ECC_SPARE 0x4
#define OP_PROGRAM_PAGE 0x6
#define OP_PAGE_PROGRAM_WITH_ECC 0x7
#define OP_PROGRAM_PAGE_SPARE 0x9
#define OP_BLOCK_ERASE 0xa
#define OP_FETCH_ID 0xb
#define OP_RESET_DEVICE 0xd
/* Default Value for NAND_DEV_CMD_VLD */
#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \
@ -692,11 +692,11 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
if (read) {
if (host->use_ecc)
cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
cmd = OP_PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
else
cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
cmd = OP_PAGE_READ | PAGE_ACC | LAST_PAGE;
} else {
cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
cmd = OP_PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
}
if (host->use_ecc) {
@ -1170,7 +1170,7 @@ static int nandc_param(struct qcom_nand_host *host)
* in use. we configure the controller to perform a raw read of 512
* bytes to read onfi params
*/
nandc_set_reg(nandc, NAND_FLASH_CMD, PAGE_READ | PAGE_ACC | LAST_PAGE);
nandc_set_reg(nandc, NAND_FLASH_CMD, OP_PAGE_READ | PAGE_ACC | LAST_PAGE);
nandc_set_reg(nandc, NAND_ADDR0, 0);
nandc_set_reg(nandc, NAND_ADDR1, 0);
nandc_set_reg(nandc, NAND_DEV0_CFG0, 0 << CW_PER_PAGE
@ -1224,7 +1224,7 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
nandc_set_reg(nandc, NAND_FLASH_CMD,
BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
nandc_set_reg(nandc, NAND_ADDR0, page_addr);
nandc_set_reg(nandc, NAND_ADDR1, 0);
nandc_set_reg(nandc, NAND_DEV0_CFG0,
@ -1255,7 +1255,7 @@ static int read_id(struct qcom_nand_host *host, int column)
if (column == -1)
return 0;
nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
nandc_set_reg(nandc, NAND_FLASH_CMD, OP_FETCH_ID);
nandc_set_reg(nandc, NAND_ADDR0, column);
nandc_set_reg(nandc, NAND_ADDR1, 0);
nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
@ -1276,7 +1276,7 @@ static int reset(struct qcom_nand_host *host)
struct nand_chip *chip = &host->chip;
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
nandc_set_reg(nandc, NAND_FLASH_CMD, OP_RESET_DEVICE);
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);

19
drivers/mtd/spi-nor/cadence-quadspi.c
View file

@ -644,9 +644,23 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor, loff_t to_addr,
ndelay(cqspi->wr_delay);
while (remaining > 0) {
size_t write_words, mod_bytes;
write_bytes = remaining > page_size ? page_size : remaining;
iowrite32_rep(cqspi->ahb_base, txbuf,
DIV_ROUND_UP(write_bytes, 4));
write_words = write_bytes / 4;
mod_bytes = write_bytes % 4;
/* Write 4 bytes at a time then single bytes. */
if (write_words) {
iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
txbuf += (write_words * 4);
}
if (mod_bytes) {
unsigned int temp = 0xFFFFFFFF;
memcpy(&temp, txbuf, mod_bytes);
iowrite32(temp, cqspi->ahb_base);
txbuf += mod_bytes;
}
if (!wait_for_completion_timeout(&cqspi->transfer_complete,
msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
@ -655,7 +669,6 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor, loff_t to_addr,
goto failwr;
}
txbuf += write_bytes;
remaining -= write_bytes;
if (remaining > 0)

1501
drivers/mtd/spi-nor/spi-nor.c
View file

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