From f37837e5474db91fe5a2a1f105be80b9ddba4813 Mon Sep 17 00:00:00 2001
From: Nitesh Gupta <nitegupt@qti.qualcomm.com>
Date: Mon, 26 Apr 2021 23:47:11 +0530
Subject: [PATCH] ARM: dts: msm: add MHI register space info for PCIe on SA6155

Add MHI register space information for PCIe so feature such as
displaying ASPM stats is possible on SA6155.

Change-Id: I17e6211165963e0ebdd170f2201cd7424e037fd1
---
 qcom/sa6155-pcie.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/qcom/sa6155-pcie.dtsi b/qcom/sa6155-pcie.dtsi
index 67b8b1a46562..42b9a8cc20a1 100644
--- a/qcom/sa6155-pcie.dtsi
+++ b/qcom/sa6155-pcie.dtsi
@@ -12,10 +12,12 @@
 			<0x40001000 0x1000>,
 			<0x40100000 0x100000>,
 			<0x40200000 0x100000>,
-			<0x40300000 0x1fd00000>;
+			<0x40300000 0x1fd00000>,
+			<0x01c0b000 0x1000>;
 
 		reg-names = "parf", "phy", "dm_core", "elbi",
-				"iatu", "conf", "io", "bars";
+				"iatu", "conf", "io", "bars",
+				"mhi";
 
 		#address-cells = <3>;
 		#size-cells = <2>;