mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 03:27:44 -04:00
ARM: SoC driver updates
Some of the larger changes this merge window:
- Removal of drivers for Exynos5440, a Samsung SoC that never saw
widespread use.
- Uniphier support for USB3 and SPI reset handling
- Syste control and SRAM drivers and bindings for Allwinner platforms
- Qualcomm AOSS (Always-on subsystem) reset controller drivers
- Raspberry Pi hwmon driver for voltage
- Mediatek pwrap (pmic) support for MT6797 SoC
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson:
"Some of the larger changes this merge window:
- Removal of drivers for Exynos5440, a Samsung SoC that never saw
widespread use.
- Uniphier support for USB3 and SPI reset handling
- Syste control and SRAM drivers and bindings for Allwinner platforms
- Qualcomm AOSS (Always-on subsystem) reset controller drivers
- Raspberry Pi hwmon driver for voltage
- Mediatek pwrap (pmic) support for MT6797 SoC"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (52 commits)
drivers/firmware: psci_checker: stash and use topology_core_cpumask for hotplug tests
soc: fsl: cleanup Kconfig menu
soc: fsl: dpio: Convert DPIO documentation to .rst
staging: fsl-mc: Remove remaining files
staging: fsl-mc: Move DPIO from staging to drivers/soc/fsl
staging: fsl-dpaa2: eth: move generic FD defines to DPIO
soc: fsl: qe: gpio: Add qe_gpio_set_multiple
usb: host: exynos: Remove support for Exynos5440
clk: samsung: Remove support for Exynos5440
soc: sunxi: Add the A13, A23 and H3 system control compatibles
reset: uniphier: add reset control support for SPI
cpufreq: exynos: Remove support for Exynos5440
ata: ahci-platform: Remove support for Exynos5440
soc: imx6qp: Use GENPD_FLAG_ALWAYS_ON for PU errata
soc: mediatek: pwrap: add mt6351 driver for mt6797 SoCs
soc: mediatek: pwrap: add pwrap driver for mt6797 SoCs
soc: mediatek: pwrap: fix cipher init setting error
dt-bindings: pwrap: mediatek: add pwrap support for MT6797
reset: uniphier: add USB3 core reset control
dt-bindings: reset: uniphier: add USB3 core reset support
...
This commit is contained in:
Linus Torvalds
commit
f3ea496213
82 changed files with 1360 additions and 880 deletions
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@ -189,7 +189,11 @@ Power-Down (SRPD), among other things.
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Required properties:
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- compatible : should contain one of these
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"brcm,brcmstb-memc-ddr-rev-b.2.1"
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"brcm,brcmstb-memc-ddr-rev-b.2.2"
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"brcm,brcmstb-memc-ddr-rev-b.2.3"
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"brcm,brcmstb-memc-ddr-rev-b.3.0"
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"brcm,brcmstb-memc-ddr-rev-b.3.1"
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"brcm,brcmstb-memc-ddr"
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- reg : the MEMC DDR register range
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@ -17,7 +17,6 @@ Required properties:
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- "marvell,armada-380-ahci"
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- "marvell,armada-3700-ahci"
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- "snps,dwc-ahci"
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- "snps,exynos5440-ahci"
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- "snps,spear-ahci"
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- "generic-ahci"
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- interrupts : <interrupt mapping for SATA IRQ>
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37
Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt
Normal file
37
Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt
Normal file
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@ -0,0 +1,37 @@
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Device tree bindings for Allwinner A64 DE2 bus
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The Allwinner A64 DE2 is on a special bus, which needs a SRAM region (SRAM C)
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to be claimed for enabling the access.
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Required properties:
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- compatible: Should contain "allwinner,sun50i-a64-de2"
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- reg: A resource specifier for the register space
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- #address-cells: Must be set to 1
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- #size-cells: Must be set to 1
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- ranges: Must be set up to map the address space inside the
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DE2, for the sub-blocks of DE2.
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- allwinner,sram: the SRAM that needs to be claimed
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Example:
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de2@1000000 {
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compatible = "allwinner,sun50i-a64-de2";
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reg = <0x1000000 0x400000>;
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allwinner,sram = <&de2_sram 1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x1000000 0x400000>;
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display_clocks: clock@0 {
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compatible = "allwinner,sun50i-a64-de2-clk";
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reg = <0x0 0x100000>;
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clocks = <&ccu CLK_DE>,
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<&ccu CLK_BUS_DE>;
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clock-names = "mod",
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"bus";
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resets = <&ccu RST_BUS_DE>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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};
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@ -36,6 +36,7 @@ Required standard properties:
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"ti,sysc-omap-aes"
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"ti,sysc-mcasp"
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"ti,sysc-usb-host-fs"
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"ti,sysc-dra7-mcan"
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- reg shall have register areas implemented for the interconnect
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target module in question such as revision, sysc and syss
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@ -1,28 +0,0 @@
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* Samsung Exynos5440 Clock Controller
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The Exynos5440 clock controller generates and supplies clock to various
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controllers within the Exynos5440 SoC.
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Required Properties:
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- compatible: should be "samsung,exynos5440-clock".
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume.
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All available clocks are defined as preprocessor macros in
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dt-bindings/clock/exynos5440.h header and can be used in device
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tree sources.
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Example: An example of a clock controller node is listed below.
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clock: clock-controller@10010000 {
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compatible = "samsung,exynos5440-clock";
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reg = <0x160000 0x10000>;
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#clock-cells = <1>;
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};
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@ -1,28 +0,0 @@
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Exynos5440 cpufreq driver
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-------------------
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Exynos5440 SoC cpufreq driver for CPU frequency scaling.
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Required properties:
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- interrupts: Interrupt to know the completion of cpu frequency change.
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- operating-points: Table of frequencies and voltage CPU could be transitioned into,
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in the decreasing order. Frequency should be in KHz units and voltage
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should be in microvolts.
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Optional properties:
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- clock-latency: Clock monitor latency in microsecond.
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All the required listed above must be defined under node cpufreq.
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Example:
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--------
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cpufreq@160000 {
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compatible = "samsung,exynos5440-cpufreq";
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reg = <0x160000 0x1000>;
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interrupts = <0 57 0>;
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operating-points = <
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1000000 975000
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800000 925000>;
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clock-latency = <100000>;
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};
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52
Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
Normal file
52
Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
Normal file
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@ -0,0 +1,52 @@
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Qualcomm AOSS Reset Controller
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======================================
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This binding describes a reset-controller found on AOSS-CC (always on subsystem)
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for Qualcomm SDM845 SoCs.
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Required properties:
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- compatible:
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Usage: required
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Value type: <string>
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Definition: must be:
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"qcom,sdm845-aoss-cc"
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: must specify the base address and size of the register
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space.
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- #reset-cells:
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Usage: required
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Value type: <uint>
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Definition: must be 1; cell entry represents the reset index.
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Example:
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aoss_reset: reset-controller@c2a0000 {
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compatible = "qcom,sdm845-aoss-cc";
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reg = <0xc2a0000 0x31000>;
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#reset-cells = <1>;
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};
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Specifying reset lines connected to IP modules
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==============================================
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Device nodes that need access to reset lines should
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specify them as a reset phandle in their corresponding node as
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specified in reset.txt.
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For list of all valid reset indicies see
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<dt-bindings/reset/qcom,sdm845-aoss.h>
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Example:
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modem-pil@4080000 {
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...
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resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
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reset-names = "mss_restart";
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...
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};
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@ -118,3 +118,59 @@ Example:
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other nodes ...
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};
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USB3 core reset
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---------------
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USB3 core reset belongs to USB3 glue layer. Before using the core reset,
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it is necessary to control the clocks and resets to enable this layer.
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These clocks and resets should be described in each property.
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Required properties:
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- compatible: Should be
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"socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC
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"socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC
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"socionext,uniphier-ld20-usb3-reset" - for LD20 SoC
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"socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC
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- #reset-cells: Should be 1.
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- reg: Specifies offset and length of the register set for the device.
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- clocks: A list of phandles to the clock gate for USB3 glue layer.
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According to the clock-names, appropriate clocks are required.
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- clock-names: Should contain
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"gio", "link" - for Pro4 SoC
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"link" - for others
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- resets: A list of phandles to the reset control for USB3 glue layer.
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According to the reset-names, appropriate resets are required.
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- reset-names: Should contain
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"gio", "link" - for Pro4 SoC
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"link" - for others
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Example:
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usb-glue@65b00000 {
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compatible = "socionext,uniphier-ld20-dwc3-glue",
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"simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65b00000 0x400>;
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usb_rst: reset@0 {
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compatible = "socionext,uniphier-ld20-usb3-reset";
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reg = <0x0 0x4>;
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#reset-cells = <1>;
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clock-names = "link";
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clocks = <&sys_clk 14>;
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reset-names = "link";
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resets = <&sys_rst 14>;
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};
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regulator {
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...
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};
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phy {
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...
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};
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...
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};
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@ -19,6 +19,7 @@ IP Pairing
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Required properties in pwrap device node.
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- compatible:
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"mediatek,mt2701-pwrap" for MT2701/7623 SoCs
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"mediatek,mt6797-pwrap" for MT6797 SoCs
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"mediatek,mt7622-pwrap" for MT7622 SoCs
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"mediatek,mt8135-pwrap" for MT8135 SoCs
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"mediatek,mt8173-pwrap" for MT8173 SoCs
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@ -10,8 +10,14 @@ Controller Node
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Required properties:
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- compatible : should be:
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- "allwinner,sun4i-a10-sram-controller"
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- "allwinner,sun50i-a64-sram-controller"
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- "allwinner,sun4i-a10-sram-controller" (deprecated)
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- "allwinner,sun4i-a10-system-control"
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- "allwinner,sun5i-a13-system-control"
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- "allwinner,sun7i-a20-system-control", "allwinner,sun4i-a10-system-control"
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- "allwinner,sun8i-a23-system-control"
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- "allwinner,sun8i-h3-system-control"
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- "allwinner,sun50i-a64-sram-controller" (deprecated)
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- "allwinner,sun50i-a64-system-control"
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- reg : sram controller register offset + length
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SRAM nodes
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@ -26,8 +32,25 @@ once again the representation described in the mmio-sram binding.
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The valid sections compatible for A10 are:
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- allwinner,sun4i-a10-sram-a3-a4
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- allwinner,sun4i-a10-sram-c1
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- allwinner,sun4i-a10-sram-d
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The valid sections compatible for A13 are:
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- allwinner,sun5i-a13-sram-a3-a4, allwinner,sun4i-a10-sram-a3-a4
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- allwinner,sun5i-a13-sram-c1, allwinner,sun4i-a10-sram-c1
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- allwinner,sun5i-a13-sram-d, allwinner,sun4i-a10-sram-d
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The valid sections compatible for A20 are:
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- allwinner,sun7i-a20-sram-a3-a4, allwinner,sun4i-a10-sram-a3-a4
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- allwinner,sun7i-a20-sram-c1, allwinner,sun4i-a10-sram-c1
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- allwinner,sun7i-a20-sram-d, allwinner,sun4i-a10-sram-d
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The valid sections compatible for A23/A33 are:
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- allwinner,sun8i-a23-sram-c1, allwinner,sun4i-a10-sram-c1
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The valid sections compatible for H3 are:
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- allwinner,sun8i-h3-sram-c1, allwinner,sun4i-a10-sram-c1
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The valid sections compatible for A64 are:
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- allwinner,sun50i-a64-sram-c
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@ -47,8 +70,8 @@ This valid values for this argument are:
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Example
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-------
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sram-controller@1c00000 {
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compatible = "allwinner,sun4i-a10-sram-controller";
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system-control@1c00000 {
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compatible = "allwinner,sun4i-a10-system-control";
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reg = <0x01c00000 0x30>;
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#address-cells = <1>;
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#size-cells = <1>;
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|
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Loading…
Reference in a new issue