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ARM: SoC driver updates

Browse source 
Some of the larger changes this merge window:
  - Removal of drivers for Exynos5440, a Samsung SoC that never saw
    widespread use.
  - Uniphier support for USB3 and SPI reset handling
  - Syste control and SRAM drivers and bindings for Allwinner platforms
  - Qualcomm AOSS (Always-on subsystem) reset controller drivers
  - Raspberry Pi hwmon driver for voltage
  - Mediatek pwrap (pmic) support for MT6797 SoC
 -----BEGIN PGP SIGNATURE-----
 
 iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAlt+MMkPHG9sb2ZAbGl4
 b20ubmV0AAoJEIwa5zzehBx3pB4QAIj7iVxSKEQFz65iXLTfMJKFZ9TSvRgWSDyE
 CHF+WOQGTnxkvySEHSw/SNqDM+Bas8ijR8b4vWzsXJFB+3HA0ZTGLU379/af1zCE
 9k8QjyIWtRWKX9fo7qCHVXlMfxGbOdbCOsh4jnmHqEIDxCHXpIiJRfvUbKIXGpfn
 tw6QpM70vm6Q6AdKwzmDbMCYnQAMWxBK/G/Q7BfRG+IYWYjFGbiWIc9BV9Ki8+nE
 3235ISaTHvAHodoec8tpLxv34GsOP4RCqscGYEuCf22RYfWva4S9e4yoWT8qPoIl
 IHWNsE3YWjksqpt9rj9Pie/PycthO4E4BUPMtqjMbC2OyKFgVsAcHrmToSdd+7ob
 t3VNM6RVl8xyWSRlm5ioev15CCOeWRi1nUT7m3UEBWpQ6ihJVpbjf1vVxZRW/E0t
 cgC+XzjSg26sWx1bSH9lGPFytOblAcZ04GG/Kpz02MmTgMiTdODFZ67AsqtdeQS7
 a9wpaQ+DgTqU0VcQx8Kdq8uy9MOztkhXn5yO8fEWjpm0lPcxjhJS4EpN+Ru2T7/Z
 AMuy5lRJfQzAPU9kY7TE0yZ07pgpZgh7LlWOoKtGD7UklzXVVZrVlpn7bApRN5vg
 ZLze5OiEiIF5gIiRC8sIyQ9TZdvg4NqwebCqspINixqs7iIpB7TG93WQcy82osSE
 TXhtx4Sy
 =ZjwY
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Olof Johansson:
 "Some of the larger changes this merge window:

   - Removal of drivers for Exynos5440, a Samsung SoC that never saw
     widespread use.

   - Uniphier support for USB3 and SPI reset handling

   - Syste control and SRAM drivers and bindings for Allwinner platforms

   - Qualcomm AOSS (Always-on subsystem) reset controller drivers

   - Raspberry Pi hwmon driver for voltage

   - Mediatek pwrap (pmic) support for MT6797 SoC"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (52 commits)
  drivers/firmware: psci_checker: stash and use topology_core_cpumask for hotplug tests
  soc: fsl: cleanup Kconfig menu
  soc: fsl: dpio: Convert DPIO documentation to .rst
  staging: fsl-mc: Remove remaining files
  staging: fsl-mc: Move DPIO from staging to drivers/soc/fsl
  staging: fsl-dpaa2: eth: move generic FD defines to DPIO
  soc: fsl: qe: gpio: Add qe_gpio_set_multiple
  usb: host: exynos: Remove support for Exynos5440
  clk: samsung: Remove support for Exynos5440
  soc: sunxi: Add the A13, A23 and H3 system control compatibles
  reset: uniphier: add reset control support for SPI
  cpufreq: exynos: Remove support for Exynos5440
  ata: ahci-platform: Remove support for Exynos5440
  soc: imx6qp: Use GENPD_FLAG_ALWAYS_ON for PU errata
  soc: mediatek: pwrap: add mt6351 driver for mt6797 SoCs
  soc: mediatek: pwrap: add pwrap driver for mt6797 SoCs
  soc: mediatek: pwrap: fix cipher init setting error
  dt-bindings: pwrap: mediatek: add pwrap support for MT6797
  reset: uniphier: add USB3 core reset control
  dt-bindings: reset: uniphier: add USB3 core reset support
  ...
This commit is contained in:
Linus Torvalds 2018-08-23 13:52:46 -07:00
commit f3ea496213
82 changed files with 1360 additions and 880 deletions
Download patch file Download diff file Expand all files Collapse all files

16
drivers/soc/bcm/brcmstb/pm/pm-arm.c
View file

@ -627,10 +627,26 @@ static const struct of_device_id ddr_shimphy_dt_ids[] = {
};
static const struct of_device_id brcmstb_memc_of_match[] = {
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1",
.data = &ddr_seq,
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2",
.data = &ddr_seq_b22,
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3",
.data = &ddr_seq_b22,
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0",
.data = &ddr_seq_b22,
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.3.1",
.data = &ddr_seq_b22,
},
{
.compatible = "brcm,brcmstb-memc-ddr",
.data = &ddr_seq,

15
drivers/soc/fsl/Kconfig
View file

@ -1,7 +1,9 @@
#
# Freescale SOC drivers
# NXP/Freescale QorIQ series SOC drivers
#
menu "NXP/Freescale QorIQ SoC drivers"
source "drivers/soc/fsl/qbman/Kconfig"
source "drivers/soc/fsl/qe/Kconfig"
@ -16,3 +18,14 @@ config FSL_GUTS
Initially only reading SVR and registering soc device are supported.
Other guts accesses, such as reading RCW, should eventually be moved
into this driver as well.
config FSL_MC_DPIO
tristate "QorIQ DPAA2 DPIO driver"
depends on FSL_MC_BUS
help
Driver for the DPAA2 DPIO object. A DPIO provides queue and
buffer management facilities for software to interact with
other DPAA2 objects. This driver does not expose the DPIO
objects individually, but groups them under a service layer
API.
endmenu

1
drivers/soc/fsl/Makefile
View file

@ -6,3 +6,4 @@ obj-$(CONFIG_FSL_DPAA) += qbman/
obj-$(CONFIG_QUICC_ENGINE) += qe/
obj-$(CONFIG_CPM) += qe/
obj-$(CONFIG_FSL_GUTS) += guts.o
obj-$(CONFIG_FSL_MC_DPIO) += dpio/

8
drivers/soc/fsl/dpio/Makefile Normal file
View file

@ -0,0 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
#
# QorIQ DPAA2 DPIO driver
#
obj-$(CONFIG_FSL_MC_DPIO) += fsl-mc-dpio.o
fsl-mc-dpio-objs := dpio.o qbman-portal.o dpio-service.o dpio-driver.o

49
drivers/soc/fsl/dpio/dpio-cmd.h Normal file
View file

@ -0,0 +1,49 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright 2013-2016 Freescale Semiconductor Inc.
* Copyright 2016 NXP
*
*/
#ifndef _FSL_DPIO_CMD_H
#define _FSL_DPIO_CMD_H
/* DPIO Version */
#define DPIO_VER_MAJOR 4
#define DPIO_VER_MINOR 2
/* Command Versioning */
#define DPIO_CMD_ID_OFFSET 4
#define DPIO_CMD_BASE_VERSION 1
#define DPIO_CMD(id) (((id) << DPIO_CMD_ID_OFFSET) | DPIO_CMD_BASE_VERSION)
/* Command IDs */
#define DPIO_CMDID_CLOSE DPIO_CMD(0x800)
#define DPIO_CMDID_OPEN DPIO_CMD(0x803)
#define DPIO_CMDID_GET_API_VERSION DPIO_CMD(0xa03)
#define DPIO_CMDID_ENABLE DPIO_CMD(0x002)
#define DPIO_CMDID_DISABLE DPIO_CMD(0x003)
#define DPIO_CMDID_GET_ATTR DPIO_CMD(0x004)
struct dpio_cmd_open {
__le32 dpio_id;
};
#define DPIO_CHANNEL_MODE_MASK 0x3
struct dpio_rsp_get_attr {
/* cmd word 0 */
__le32 id;
__le16 qbman_portal_id;
u8 num_priorities;
u8 channel_mode;
/* cmd word 1 */
__le64 qbman_portal_ce_addr;
/* cmd word 2 */
__le64 qbman_portal_ci_addr;
/* cmd word 3 */
__le32 qbman_version;
};
#endif /* _FSL_DPIO_CMD_H */

281
drivers/soc/fsl/dpio/dpio-driver.c Normal file
View file

@ -0,0 +1,281 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2014-2016 Freescale Semiconductor Inc.
* Copyright NXP 2016
*
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/msi.h>
#include <linux/dma-mapping.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/fsl/mc.h>
#include <soc/fsl/dpaa2-io.h>
#include "qbman-portal.h"
#include "dpio.h"
#include "dpio-cmd.h"
MODULE_LICENSE("Dual BSD/GPL");
MODULE_AUTHOR("Freescale Semiconductor, Inc");
MODULE_DESCRIPTION("DPIO Driver");
struct dpio_priv {
struct dpaa2_io *io;
};
static irqreturn_t dpio_irq_handler(int irq_num, void *arg)
{
struct device *dev = (struct device *)arg;
struct dpio_priv *priv = dev_get_drvdata(dev);
return dpaa2_io_irq(priv->io);
}
static void unregister_dpio_irq_handlers(struct fsl_mc_device *dpio_dev)
{
struct fsl_mc_device_irq *irq;
irq = dpio_dev->irqs[0];
/* clear the affinity hint */
irq_set_affinity_hint(irq->msi_desc->irq, NULL);
}
static int register_dpio_irq_handlers(struct fsl_mc_device *dpio_dev, int cpu)
{
struct dpio_priv *priv;
int error;
struct fsl_mc_device_irq *irq;
cpumask_t mask;
priv = dev_get_drvdata(&dpio_dev->dev);
irq = dpio_dev->irqs[0];
error = devm_request_irq(&dpio_dev->dev,
irq->msi_desc->irq,
dpio_irq_handler,
0,
dev_name(&dpio_dev->dev),
&dpio_dev->dev);
if (error < 0) {
dev_err(&dpio_dev->dev,
"devm_request_irq() failed: %d\n",
error);
return error;
}
/* set the affinity hint */
cpumask_clear(&mask);
cpumask_set_cpu(cpu, &mask);
if (irq_set_affinity_hint(irq->msi_desc->irq, &mask))
dev_err(&dpio_dev->dev,
"irq_set_affinity failed irq %d cpu %d\n",
irq->msi_desc->irq, cpu);
return 0;
}
static int dpaa2_dpio_probe(struct fsl_mc_device *dpio_dev)
{
struct dpio_attr dpio_attrs;
struct dpaa2_io_desc desc;
struct dpio_priv *priv;
int err = -ENOMEM;
struct device *dev = &dpio_dev->dev;
static int next_cpu = -1;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
goto err_priv_alloc;
dev_set_drvdata(dev, priv);
err = fsl_mc_portal_allocate(dpio_dev, 0, &dpio_dev->mc_io);
if (err) {
dev_dbg(dev, "MC portal allocation failed\n");
err = -EPROBE_DEFER;
goto err_priv_alloc;
}
err = dpio_open(dpio_dev->mc_io, 0, dpio_dev->obj_desc.id,
&dpio_dev->mc_handle);
if (err) {
dev_err(dev, "dpio_open() failed\n");
goto err_open;
}
err = dpio_get_attributes(dpio_dev->mc_io, 0, dpio_dev->mc_handle,
&dpio_attrs);
if (err) {
dev_err(dev, "dpio_get_attributes() failed %d\n", err);
goto err_get_attr;
}
desc.qman_version = dpio_attrs.qbman_version;
err = dpio_enable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
if (err) {
dev_err(dev, "dpio_enable() failed %d\n", err);
goto err_get_attr;
}
/* initialize DPIO descriptor */
desc.receives_notifications = dpio_attrs.num_priorities ? 1 : 0;
desc.has_8prio = dpio_attrs.num_priorities == 8 ? 1 : 0;
desc.dpio_id = dpio_dev->obj_desc.id;
/* get the cpu to use for the affinity hint */
if (next_cpu == -1)
next_cpu = cpumask_first(cpu_online_mask);
else
next_cpu = cpumask_next(next_cpu, cpu_online_mask);
if (!cpu_possible(next_cpu)) {
dev_err(dev, "probe failed. Number of DPIOs exceeds NR_CPUS.\n");
err = -ERANGE;
goto err_allocate_irqs;
}
desc.cpu = next_cpu;
/*
* Set the CENA regs to be the cache inhibited area of the portal to
* avoid coherency issues if a user migrates to another core.
*/
desc.regs_cena = devm_memremap(dev, dpio_dev->regions[1].start,
resource_size(&dpio_dev->regions[1]),
MEMREMAP_WC);
if (IS_ERR(desc.regs_cena)) {
dev_err(dev, "devm_memremap failed\n");
err = PTR_ERR(desc.regs_cena);
goto err_allocate_irqs;
}
desc.regs_cinh = devm_ioremap(dev, dpio_dev->regions[1].start,
resource_size(&dpio_dev->regions[1]));
if (!desc.regs_cinh) {
err = -ENOMEM;
dev_err(dev, "devm_ioremap failed\n");
goto err_allocate_irqs;
}
err = fsl_mc_allocate_irqs(dpio_dev);
if (err) {
dev_err(dev, "fsl_mc_allocate_irqs failed. err=%d\n", err);
goto err_allocate_irqs;
}
err = register_dpio_irq_handlers(dpio_dev, desc.cpu);
if (err)
goto err_register_dpio_irq;
priv->io = dpaa2_io_create(&desc);
if (!priv->io) {
dev_err(dev, "dpaa2_io_create failed\n");
err = -ENOMEM;
goto err_dpaa2_io_create;
}
dev_info(dev, "probed\n");
dev_dbg(dev, " receives_notifications = %d\n",
desc.receives_notifications);
dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
fsl_mc_portal_free(dpio_dev->mc_io);
return 0;
err_dpaa2_io_create:
unregister_dpio_irq_handlers(dpio_dev);
err_register_dpio_irq:
fsl_mc_free_irqs(dpio_dev);
err_allocate_irqs:
dpio_disable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
err_get_attr:
dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
err_open:
fsl_mc_portal_free(dpio_dev->mc_io);
err_priv_alloc:
return err;
}
/* Tear down interrupts for a given DPIO object */
static void dpio_teardown_irqs(struct fsl_mc_device *dpio_dev)
{
unregister_dpio_irq_handlers(dpio_dev);
fsl_mc_free_irqs(dpio_dev);
}
static int dpaa2_dpio_remove(struct fsl_mc_device *dpio_dev)
{
struct device *dev;
struct dpio_priv *priv;
int err;
dev = &dpio_dev->dev;
priv = dev_get_drvdata(dev);
dpaa2_io_down(priv->io);
dpio_teardown_irqs(dpio_dev);
err = fsl_mc_portal_allocate(dpio_dev, 0, &dpio_dev->mc_io);
if (err) {
dev_err(dev, "MC portal allocation failed\n");
goto err_mcportal;
}
err = dpio_open(dpio_dev->mc_io, 0, dpio_dev->obj_desc.id,
&dpio_dev->mc_handle);
if (err) {
dev_err(dev, "dpio_open() failed\n");
goto err_open;
}
dpio_disable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
fsl_mc_portal_free(dpio_dev->mc_io);
return 0;
err_open:
fsl_mc_portal_free(dpio_dev->mc_io);
err_mcportal:
return err;
}
static const struct fsl_mc_device_id dpaa2_dpio_match_id_table[] = {
{
.vendor = FSL_MC_VENDOR_FREESCALE,
.obj_type = "dpio",
},
{ .vendor = 0x0 }
};
static struct fsl_mc_driver dpaa2_dpio_driver = {
.driver = {
.name = KBUILD_MODNAME,
.owner = THIS_MODULE,
},
.probe = dpaa2_dpio_probe,
.remove = dpaa2_dpio_remove,
.match_id_table = dpaa2_dpio_match_id_table
};
static int dpio_driver_init(void)
{
return fsl_mc_driver_register(&dpaa2_dpio_driver);
}
static void dpio_driver_exit(void)
{
fsl_mc_driver_unregister(&dpaa2_dpio_driver);
}
module_init(dpio_driver_init);
module_exit(dpio_driver_exit);

545
drivers/soc/fsl/dpio/dpio-service.c Normal file
View file

@ -0,0 +1,545 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2014-2016 Freescale Semiconductor Inc.
* Copyright 2016 NXP
*
*/
#include <linux/types.h>
#include <linux/fsl/mc.h>
#include <soc/fsl/dpaa2-io.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include "dpio.h"
#include "qbman-portal.h"
struct dpaa2_io {
struct dpaa2_io_desc dpio_desc;
struct qbman_swp_desc swp_desc;
struct qbman_swp *swp;
struct list_head node;
/* protect against multiple management commands */
spinlock_t lock_mgmt_cmd;
/* protect notifications list */
spinlock_t lock_notifications;
struct list_head notifications;
};
struct dpaa2_io_store {
unsigned int max;
dma_addr_t paddr;
struct dpaa2_dq *vaddr;
void *alloced_addr; /* unaligned value from kmalloc() */
unsigned int idx; /* position of the next-to-be-returned entry */
struct qbman_swp *swp; /* portal used to issue VDQCR */
struct device *dev; /* device used for DMA mapping */
};
/* keep a per cpu array of DPIOs for fast access */
static struct dpaa2_io *dpio_by_cpu[NR_CPUS];
static struct list_head dpio_list = LIST_HEAD_INIT(dpio_list);
static DEFINE_SPINLOCK(dpio_list_lock);
static inline struct dpaa2_io *service_select_by_cpu(struct dpaa2_io *d,
int cpu)
{
if (d)
return d;
if (cpu != DPAA2_IO_ANY_CPU && cpu >= num_possible_cpus())
return NULL;
/*
* If cpu == -1, choose the current cpu, with no guarantees about
* potentially being migrated away.
*/
if (unlikely(cpu < 0))
cpu = smp_processor_id();
/* If a specific cpu was requested, pick it up immediately */
return dpio_by_cpu[cpu];
}
static inline struct dpaa2_io *service_select(struct dpaa2_io *d)
{
if (d)
return d;
spin_lock(&dpio_list_lock);
d = list_entry(dpio_list.next, struct dpaa2_io, node);
list_del(&d->node);
list_add_tail(&d->node, &dpio_list);
spin_unlock(&dpio_list_lock);
return d;
}
/**
* dpaa2_io_service_select() - return a dpaa2_io service affined to this cpu
* @cpu: the cpu id
*
* Return the affine dpaa2_io service, or NULL if there is no service affined
* to the specified cpu. If DPAA2_IO_ANY_CPU is used, return the next available
* service.
*/
struct dpaa2_io *dpaa2_io_service_select(int cpu)
{
if (cpu == DPAA2_IO_ANY_CPU)
return service_select(NULL);
return service_select_by_cpu(NULL, cpu);
}
EXPORT_SYMBOL_GPL(dpaa2_io_service_select);
/**
* dpaa2_io_create() - create a dpaa2_io object.
* @desc: the dpaa2_io descriptor
*
* Activates a "struct dpaa2_io" corresponding to the given config of an actual
* DPIO object.
*
* Return a valid dpaa2_io object for success, or NULL for failure.
*/
struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc)
{
struct dpaa2_io *obj = kmalloc(sizeof(*obj), GFP_KERNEL);
if (!obj)
return NULL;
/* check if CPU is out of range (-1 means any cpu) */
if (desc->cpu != DPAA2_IO_ANY_CPU && desc->cpu >= num_possible_cpus()) {
kfree(obj);
return NULL;
}
obj->dpio_desc = *desc;
obj->swp_desc.cena_bar = obj->dpio_desc.regs_cena;
obj->swp_desc.cinh_bar = obj->dpio_desc.regs_cinh;
obj->swp_desc.qman_version = obj->dpio_desc.qman_version;
obj->swp = qbman_swp_init(&obj->swp_desc);
if (!obj->swp) {
kfree(obj);
return NULL;
}
INIT_LIST_HEAD(&obj->node);
spin_lock_init(&obj->lock_mgmt_cmd);
spin_lock_init(&obj->lock_notifications);
INIT_LIST_HEAD(&obj->notifications);
/* For now only enable DQRR interrupts */
qbman_swp_interrupt_set_trigger(obj->swp,
QBMAN_SWP_INTERRUPT_DQRI);
qbman_swp_interrupt_clear_status(obj->swp, 0xffffffff);
if (obj->dpio_desc.receives_notifications)
qbman_swp_push_set(obj->swp, 0, 1);
spin_lock(&dpio_list_lock);
list_add_tail(&obj->node, &dpio_list);
if (desc->cpu >= 0 && !dpio_by_cpu[desc->cpu])
dpio_by_cpu[desc->cpu] = obj;
spin_unlock(&dpio_list_lock);
return obj;
}
/**
* dpaa2_io_down() - release the dpaa2_io object.
* @d: the dpaa2_io object to be released.
*
* The "struct dpaa2_io" type can represent an individual DPIO object (as
* described by "struct dpaa2_io_desc") or an instance of a "DPIO service",
* which can be used to group/encapsulate multiple DPIO objects. In all cases,
* each handle obtained should be released using this function.
*/
void dpaa2_io_down(struct dpaa2_io *d)
{
kfree(d);
}
#define DPAA_POLL_MAX 32
/**
* dpaa2_io_irq() - ISR for DPIO interrupts
*
* @obj: the given DPIO object.
*
* Return IRQ_HANDLED for success or IRQ_NONE if there
* were no pending interrupts.
*/
irqreturn_t dpaa2_io_irq(struct dpaa2_io *obj)
{
const struct dpaa2_dq *dq;
int max = 0;
struct qbman_swp *swp;
u32 status;
swp = obj->swp;
status = qbman_swp_interrupt_read_status(swp);
if (!status)
return IRQ_NONE;
dq = qbman_swp_dqrr_next(swp);
while (dq) {
if (qbman_result_is_SCN(dq)) {
struct dpaa2_io_notification_ctx *ctx;
u64 q64;
q64 = qbman_result_SCN_ctx(dq);
ctx = (void *)(uintptr_t)q64;
ctx->cb(ctx);
} else {
pr_crit("fsl-mc-dpio: Unrecognised/ignored DQRR entry\n");
}
qbman_swp_dqrr_consume(swp, dq);
++max;
if (max > DPAA_POLL_MAX)
goto done;
dq = qbman_swp_dqrr_next(swp);
}
done:
qbman_swp_interrupt_clear_status(swp, status);
qbman_swp_interrupt_set_inhibit(swp, 0);
return IRQ_HANDLED;
}
/**
* dpaa2_io_service_register() - Prepare for servicing of FQDAN or CDAN
* notifications on the given DPIO service.
* @d: the given DPIO service.
* @ctx: the notification context.
*
* The caller should make the MC command to attach a DPAA2 object to
* a DPIO after this function completes successfully. In that way:
* (a) The DPIO service is "ready" to handle a notification arrival
* (which might happen before the "attach" command to MC has
* returned control of execution back to the caller)
* (b) The DPIO service can provide back to the caller the 'dpio_id' and
* 'qman64' parameters that it should pass along in the MC command
* in order for the object to be configured to produce the right
* notification fields to the DPIO service.
*
* Return 0 for success, or -ENODEV for failure.
*/
int dpaa2_io_service_register(struct dpaa2_io *d,
struct dpaa2_io_notification_ctx *ctx)
{
unsigned long irqflags;
d = service_select_by_cpu(d, ctx->desired_cpu);
if (!d)
return -ENODEV;
ctx->dpio_id = d->dpio_desc.dpio_id;
ctx->qman64 = (u64)(uintptr_t)ctx;
ctx->dpio_private = d;
spin_lock_irqsave(&d->lock_notifications, irqflags);
list_add(&ctx->node, &d->notifications);
spin_unlock_irqrestore(&d->lock_notifications, irqflags);
/* Enable the generation of CDAN notifications */
if (ctx->is_cdan)
return qbman_swp_CDAN_set_context_enable(d->swp,
(u16)ctx->id,
ctx->qman64);
return 0;
}
EXPORT_SYMBOL_GPL(dpaa2_io_service_register);
/**
* dpaa2_io_service_deregister - The opposite of 'register'.
* @service: the given DPIO service.
* @ctx: the notification context.
*
* This function should be called only after sending the MC command to
* to detach the notification-producing device from the DPIO.
*/
void dpaa2_io_service_deregister(struct dpaa2_io *service,
struct dpaa2_io_notification_ctx *ctx)
{
struct dpaa2_io *d = ctx->dpio_private;
unsigned long irqflags;
if (ctx->is_cdan)
qbman_swp_CDAN_disable(d->swp, (u16)ctx->id);
spin_lock_irqsave(&d->lock_notifications, irqflags);
list_del(&ctx->node);
spin_unlock_irqrestore(&d->lock_notifications, irqflags);
}
EXPORT_SYMBOL_GPL(dpaa2_io_service_deregister);
/**
* dpaa2_io_service_rearm() - Rearm the notification for the given DPIO service.
* @d: the given DPIO service.
* @ctx: the notification context.
*
* Once a FQDAN/CDAN has been produced, the corresponding FQ/channel is
* considered "disarmed". Ie. the user can issue pull dequeue operations on that
* traffic source for as long as it likes. Eventually it may wish to "rearm"
* that source to allow it to produce another FQDAN/CDAN, that's what this
* function achieves.
*
* Return 0 for success.
*/
int dpaa2_io_service_rearm(struct dpaa2_io *d,
struct dpaa2_io_notification_ctx *ctx)
{
unsigned long irqflags;
int err;
d = service_select_by_cpu(d, ctx->desired_cpu);
if (!unlikely(d))
return -ENODEV;
spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
if (ctx->is_cdan)
err = qbman_swp_CDAN_enable(d->swp, (u16)ctx->id);
else
err = qbman_swp_fq_schedule(d->swp, ctx->id);
spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
return err;
}
EXPORT_SYMBOL_GPL(dpaa2_io_service_rearm);
/**
* dpaa2_io_service_pull_channel() - pull dequeue functions from a channel.
* @d: the given DPIO service.
* @channelid: the given channel id.
* @s: the dpaa2_io_store object for the result.
*
* Return 0 for success, or error code for failure.
*/
int dpaa2_io_service_pull_channel(struct dpaa2_io *d, u32 channelid,
struct dpaa2_io_store *s)
{
struct qbman_pull_desc pd;
int err;
qbman_pull_desc_clear(&pd);
qbman_pull_desc_set_storage(&pd, s->vaddr, s->paddr, 1);
qbman_pull_desc_set_numframes(&pd, (u8)s->max);
qbman_pull_desc_set_channel(&pd, channelid, qbman_pull_type_prio);
d = service_select(d);
if (!d)
return -ENODEV;
s->swp = d->swp;
err = qbman_swp_pull(d->swp, &pd);
if (err)
s->swp = NULL;
return err;
}
EXPORT_SYMBOL_GPL(dpaa2_io_service_pull_channel);
/**
* dpaa2_io_service_enqueue_qd() - Enqueue a frame to a QD.
* @d: the given DPIO service.
* @qdid: the given queuing destination id.
* @prio: the given queuing priority.
* @qdbin: the given queuing destination bin.
* @fd: the frame descriptor which is enqueued.
*
* Return 0 for successful enqueue, or -EBUSY if the enqueue ring is not ready,
* or -ENODEV if there is no dpio service.
*/
int dpaa2_io_service_enqueue_qd(struct dpaa2_io *d,
u32 qdid, u8 prio, u16 qdbin,
const struct dpaa2_fd *fd)
{
struct qbman_eq_desc ed;
d = service_select(d);
if (!d)
return -ENODEV;
qbman_eq_desc_clear(&ed);
qbman_eq_desc_set_no_orp(&ed, 0);
qbman_eq_desc_set_qd(&ed, qdid, qdbin, prio);
return qbman_swp_enqueue(d->swp, &ed, fd);
}
EXPORT_SYMBOL_GPL(dpaa2_io_service_enqueue_qd);
/**
* dpaa2_io_service_release() - Release buffers to a buffer pool.
* @d: the given DPIO object.
* @bpid: the buffer pool id.
* @buffers: the buffers to be released.
* @num_buffers: the number of the buffers to be released.
*
* Return 0 for success, and negative error code for failure.
*/
int dpaa2_io_service_release(struct dpaa2_io *d,
u32 bpid,
const u64 *buffers,
unsigned int num_buffers)
{
struct qbman_release_desc rd;
d = service_select(d);
if (!d)
return -ENODEV;
qbman_release_desc_clear(&rd);
qbman_release_desc_set_bpid(&rd, bpid);
return qbman_swp_release(d->swp, &rd, buffers, num_buffers);
}
EXPORT_SYMBOL_GPL(dpaa2_io_service_release);
/**
* dpaa2_io_service_acquire() - Acquire buffers from a buffer pool.
* @d: the given DPIO object.
* @bpid: the buffer pool id.
* @buffers: the buffer addresses for acquired buffers.
* @num_buffers: the expected number of the buffers to acquire.
*
* Return a negative error code if the command failed, otherwise it returns
* the number of buffers acquired, which may be less than the number requested.
* Eg. if the buffer pool is empty, this will return zero.
*/
int dpaa2_io_service_acquire(struct dpaa2_io *d,
u32 bpid,
u64 *buffers,
unsigned int num_buffers)
{
unsigned long irqflags;
int err;
d = service_select(d);
if (!d)
return -ENODEV;
spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
err = qbman_swp_acquire(d->swp, bpid, buffers, num_buffers);
spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
return err;
}
EXPORT_SYMBOL_GPL(dpaa2_io_service_acquire);
/*
* 'Stores' are reusable memory blocks for holding dequeue results, and to
* assist with parsing those results.
*/
/**
* dpaa2_io_store_create() - Create the dma memory storage for dequeue result.
* @max_frames: the maximum number of dequeued result for frames, must be <= 16.
* @dev: the device to allow mapping/unmapping the DMAable region.
*
* The size of the storage is "max_frames*sizeof(struct dpaa2_dq)".
* The 'dpaa2_io_store' returned is a DPIO service managed object.
*
* Return pointer to dpaa2_io_store struct for successfully created storage
* memory, or NULL on error.
*/
struct dpaa2_io_store *dpaa2_io_store_create(unsigned int max_frames,
struct device *dev)
{
struct dpaa2_io_store *ret;
size_t size;
if (!max_frames || (max_frames > 16))
return NULL;
ret = kmalloc(sizeof(*ret), GFP_KERNEL);
if (!ret)
return NULL;
ret->max = max_frames;
size = max_frames * sizeof(struct dpaa2_dq) + 64;
ret->alloced_addr = kzalloc(size, GFP_KERNEL);
if (!ret->alloced_addr) {
kfree(ret);
return NULL;
}
ret->vaddr = PTR_ALIGN(ret->alloced_addr, 64);
ret->paddr = dma_map_single(dev, ret->vaddr,
sizeof(struct dpaa2_dq) * max_frames,
DMA_FROM_DEVICE);
if (dma_mapping_error(dev, ret->paddr)) {
kfree(ret->alloced_addr);
kfree(ret);
return NULL;
}
ret->idx = 0;
ret->dev = dev;
return ret;
}
EXPORT_SYMBOL_GPL(dpaa2_io_store_create);
/**
* dpaa2_io_store_destroy() - Frees the dma memory storage for dequeue
* result.
* @s: the storage memory to be destroyed.
*/
void dpaa2_io_store_destroy(struct dpaa2_io_store *s)
{
dma_unmap_single(s->dev, s->paddr, sizeof(struct dpaa2_dq) * s->max,
DMA_FROM_DEVICE);
kfree(s->alloced_addr);
kfree(s);
}
EXPORT_SYMBOL_GPL(dpaa2_io_store_destroy);
/**
* dpaa2_io_store_next() - Determine when the next dequeue result is available.
* @s: the dpaa2_io_store object.
* @is_last: indicate whether this is the last frame in the pull command.
*
* When an object driver performs dequeues to a dpaa2_io_store, this function
* can be used to determine when the next frame result is available. Once
* this function returns non-NULL, a subsequent call to it will try to find
* the next dequeue result.
*
* Note that if a pull-dequeue has a NULL result because the target FQ/channel
* was empty, then this function will also return NULL (rather than expecting
* the caller to always check for this. As such, "is_last" can be used to
* differentiate between "end-of-empty-dequeue" and "still-waiting".
*
* Return dequeue result for a valid dequeue result, or NULL for empty dequeue.
*/
struct dpaa2_dq *dpaa2_io_store_next(struct dpaa2_io_store *s, int *is_last)
{
int match;
struct dpaa2_dq *ret = &s->vaddr[s->idx];
match = qbman_result_has_new_result(s->swp, ret);
if (!match) {
*is_last = 0;
return NULL;
}
s->idx++;
if (dpaa2_dq_is_pull_complete(ret)) {
*is_last = 1;
s->idx = 0;
/*
* If we get an empty dequeue result to terminate a zero-results
* vdqcr, return NULL to the caller rather than expecting him to
* check non-NULL results every time.
*/
if (!(dpaa2_dq_flags(ret) & DPAA2_DQ_STAT_VALIDFRAME))
ret = NULL;
} else {
*is_last = 0;
}
return ret;
}
EXPORT_SYMBOL_GPL(dpaa2_io_store_next);

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2013-2016 Freescale Semiconductor Inc.
* Copyright 2016 NXP
*
*/
#include <linux/kernel.h>
#include <linux/fsl/mc.h>
#include "dpio.h"
#include "dpio-cmd.h"
/*
* Data Path I/O Portal API
* Contains initialization APIs and runtime control APIs for DPIO
*/
/**
* dpio_open() - Open a control session for the specified object
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @dpio_id: DPIO unique ID
* @token: Returned token; use in subsequent API calls
*
* This function can be used to open a control session for an
* already created object; an object may have been declared in
* the DPL or by calling the dpio_create() function.
* This function returns a unique authentication token,
* associated with the specific object ID and the specific MC
* portal; this token must be used in all subsequent commands for
* this specific object.
*
* Return: '0' on Success; Error code otherwise.
*/
int dpio_open(struct fsl_mc_io *mc_io,
u32 cmd_flags,
int dpio_id,
u16 *token)
{
struct fsl_mc_command cmd = { 0 };
struct dpio_cmd_open *dpio_cmd;
int err;
/* prepare command */
cmd.header = mc_encode_cmd_header(DPIO_CMDID_OPEN,
cmd_flags,
0);
dpio_cmd = (struct dpio_cmd_open *)cmd.params;
dpio_cmd->dpio_id = cpu_to_le32(dpio_id);
err = mc_send_command(mc_io, &cmd);
if (err)
return err;
/* retrieve response parameters */
*token = mc_cmd_hdr_read_token(&cmd);
return 0;
}
/**
* dpio_close() - Close the control session of the object
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPIO object
*
* Return: '0' on Success; Error code otherwise.
*/
int dpio_close(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token)
{
struct fsl_mc_command cmd = { 0 };
/* prepare command */
cmd.header = mc_encode_cmd_header(DPIO_CMDID_CLOSE,
cmd_flags,
token);
return mc_send_command(mc_io, &cmd);
}
/**
* dpio_enable() - Enable the DPIO, allow I/O portal operations.
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPIO object
*
* Return: '0' on Success; Error code otherwise
*/
int dpio_enable(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token)
{
struct fsl_mc_command cmd = { 0 };
/* prepare command */
cmd.header = mc_encode_cmd_header(DPIO_CMDID_ENABLE,
cmd_flags,
token);
return mc_send_command(mc_io, &cmd);
}
/**
* dpio_disable() - Disable the DPIO, stop any I/O portal operation.
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPIO object
*
* Return: '0' on Success; Error code otherwise
*/
int dpio_disable(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token)
{
struct fsl_mc_command cmd = { 0 };
/* prepare command */
cmd.header = mc_encode_cmd_header(DPIO_CMDID_DISABLE,
cmd_flags,
token);
return mc_send_command(mc_io, &cmd);
}
/**
* dpio_get_attributes() - Retrieve DPIO attributes
* @mc_io: Pointer to MC portal's I/O object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @token: Token of DPIO object
* @attr: Returned object's attributes
*
* Return: '0' on Success; Error code otherwise
*/
int dpio_get_attributes(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
struct dpio_attr *attr)
{
struct fsl_mc_command cmd = { 0 };
struct dpio_rsp_get_attr *dpio_rsp;
int err;
/* prepare command */
cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_ATTR,
cmd_flags,
token);
err = mc_send_command(mc_io, &cmd);
if (err)
return err;
/* retrieve response parameters */
dpio_rsp = (struct dpio_rsp_get_attr *)cmd.params;
attr->id = le32_to_cpu(dpio_rsp->id);
attr->qbman_portal_id = le16_to_cpu(dpio_rsp->qbman_portal_id);
attr->num_priorities = dpio_rsp->num_priorities;
attr->channel_mode = dpio_rsp->channel_mode & DPIO_CHANNEL_MODE_MASK;
attr->qbman_portal_ce_offset =
le64_to_cpu(dpio_rsp->qbman_portal_ce_addr);
attr->qbman_portal_ci_offset =
le64_to_cpu(dpio_rsp->qbman_portal_ci_addr);
attr->qbman_version = le32_to_cpu(dpio_rsp->qbman_version);
return 0;
}
/**
* dpio_get_api_version - Get Data Path I/O API version
* @mc_io: Pointer to MC portal's DPIO object
* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
* @major_ver: Major version of DPIO API
* @minor_ver: Minor version of DPIO API
*
* Return: '0' on Success; Error code otherwise
*/
int dpio_get_api_version(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 *major_ver,
u16 *minor_ver)
{
struct fsl_mc_command cmd = { 0 };
int err;
/* prepare command */
cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_API_VERSION,
cmd_flags, 0);
err = mc_send_command(mc_io, &cmd);
if (err)
return err;
/* retrieve response parameters */
mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
return 0;
}

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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright 2013-2016 Freescale Semiconductor Inc.
* Copyright 2016 NXP
*
*/
#ifndef __FSL_DPIO_H
#define __FSL_DPIO_H
struct fsl_mc_io;
int dpio_open(struct fsl_mc_io *mc_io,
u32 cmd_flags,
int dpio_id,
u16 *token);
int dpio_close(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token);
/**
* enum dpio_channel_mode - DPIO notification channel mode
* @DPIO_NO_CHANNEL: No support for notification channel
* @DPIO_LOCAL_CHANNEL: Notifications on data availability can be received by a
* dedicated channel in the DPIO; user should point the queue's
* destination in the relevant interface to this DPIO
*/
enum dpio_channel_mode {
DPIO_NO_CHANNEL = 0,
DPIO_LOCAL_CHANNEL = 1,
};
/**
* struct dpio_cfg - Structure representing DPIO configuration
* @channel_mode: Notification channel mode
* @num_priorities: Number of priorities for the notification channel (1-8);
* relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
*/
struct dpio_cfg {
enum dpio_channel_mode channel_mode;
u8 num_priorities;
};
int dpio_enable(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token);
int dpio_disable(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token);
/**
* struct dpio_attr - Structure representing DPIO attributes
* @id: DPIO object ID
* @qbman_portal_ce_offset: offset of the software portal cache-enabled area
* @qbman_portal_ci_offset: offset of the software portal cache-inhibited area
* @qbman_portal_id: Software portal ID
* @channel_mode: Notification channel mode
* @num_priorities: Number of priorities for the notification channel (1-8);
* relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
* @qbman_version: QBMAN version
*/
struct dpio_attr {
int id;
u64 qbman_portal_ce_offset;
u64 qbman_portal_ci_offset;
u16 qbman_portal_id;
enum dpio_channel_mode channel_mode;
u8 num_priorities;
u32 qbman_version;
};
int dpio_get_attributes(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
struct dpio_attr *attr);
int dpio_get_api_version(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 *major_ver,
u16 *minor_ver);
#endif /* __FSL_DPIO_H */

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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
* Copyright 2016 NXP
*
*/
#ifndef __FSL_QBMAN_PORTAL_H
#define __FSL_QBMAN_PORTAL_H
#include <soc/fsl/dpaa2-fd.h>
struct dpaa2_dq;
struct qbman_swp;
/* qbman software portal descriptor structure */
struct qbman_swp_desc {
void *cena_bar; /* Cache-enabled portal base address */
void __iomem *cinh_bar; /* Cache-inhibited portal base address */
u32 qman_version;
};
#define QBMAN_SWP_INTERRUPT_EQRI 0x01
#define QBMAN_SWP_INTERRUPT_EQDI 0x02
#define QBMAN_SWP_INTERRUPT_DQRI 0x04
#define QBMAN_SWP_INTERRUPT_RCRI 0x08
#define QBMAN_SWP_INTERRUPT_RCDI 0x10
#define QBMAN_SWP_INTERRUPT_VDCI 0x20
/* the structure for pull dequeue descriptor */
struct qbman_pull_desc {
u8 verb;
u8 numf;
u8 tok;
u8 reserved;
__le32 dq_src;
__le64 rsp_addr;
u64 rsp_addr_virt;
u8 padding[40];
};
enum qbman_pull_type_e {
/* dequeue with priority precedence, respect intra-class scheduling */
qbman_pull_type_prio = 1,
/* dequeue with active FQ precedence, respect ICS */
qbman_pull_type_active,
/* dequeue with active FQ precedence, no ICS */
qbman_pull_type_active_noics
};
/* Definitions for parsing dequeue entries */
#define QBMAN_RESULT_MASK 0x7f
#define QBMAN_RESULT_DQ 0x60
#define QBMAN_RESULT_FQRN 0x21
#define QBMAN_RESULT_FQRNI 0x22
#define QBMAN_RESULT_FQPN 0x24
#define QBMAN_RESULT_FQDAN 0x25
#define QBMAN_RESULT_CDAN 0x26
#define QBMAN_RESULT_CSCN_MEM 0x27
#define QBMAN_RESULT_CGCU 0x28
#define QBMAN_RESULT_BPSCN 0x29
#define QBMAN_RESULT_CSCN_WQ 0x2a
/* QBMan FQ management command codes */
#define QBMAN_FQ_SCHEDULE 0x48
#define QBMAN_FQ_FORCE 0x49
#define QBMAN_FQ_XON 0x4d
#define QBMAN_FQ_XOFF 0x4e
/* structure of enqueue descriptor */
struct qbman_eq_desc {
u8 verb;
u8 dca;
__le16 seqnum;
__le16 orpid;
__le16 reserved1;
__le32 tgtid;
__le32 tag;
__le16 qdbin;
u8 qpri;
u8 reserved[3];
u8 wae;
u8 rspid;
__le64 rsp_addr;
u8 fd[32];
};
/* buffer release descriptor */
struct qbman_release_desc {
u8 verb;
u8 reserved;
__le16 bpid;
__le32 reserved2;
__le64 buf[7];
};
/* Management command result codes */
#define QBMAN_MC_RSLT_OK 0xf0
#define CODE_CDAN_WE_EN 0x1
#define CODE_CDAN_WE_CTX 0x4
/* portal data structure */
struct qbman_swp {
const struct qbman_swp_desc *desc;
void *addr_cena;
void __iomem *addr_cinh;
/* Management commands */
struct {
u32 valid_bit; /* 0x00 or 0x80 */
} mc;
/* Push dequeues */
u32 sdq;
/* Volatile dequeues */
struct {
atomic_t available; /* indicates if a command can be sent */
u32 valid_bit; /* 0x00 or 0x80 */
struct dpaa2_dq *storage; /* NULL if DQRR */
} vdq;
/* DQRR */
struct {
u32 next_idx;
u32 valid_bit;
u8 dqrr_size;
int reset_bug; /* indicates dqrr reset workaround is needed */
} dqrr;
};
struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d);
void qbman_swp_finish(struct qbman_swp *p);
u32 qbman_swp_interrupt_read_status(struct qbman_swp *p);
void qbman_swp_interrupt_clear_status(struct qbman_swp *p, u32 mask);
u32 qbman_swp_interrupt_get_trigger(struct qbman_swp *p);
void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, u32 mask);
int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p);
void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit);
void qbman_swp_push_get(struct qbman_swp *p, u8 channel_idx, int *enabled);
void qbman_swp_push_set(struct qbman_swp *p, u8 channel_idx, int enable);
void qbman_pull_desc_clear(struct qbman_pull_desc *d);
void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
struct dpaa2_dq *storage,
dma_addr_t storage_phys,
int stash);
void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, u8 numframes);
void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, u32 fqid);
void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, u32 wqid,
enum qbman_pull_type_e dct);
void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, u32 chid,
enum qbman_pull_type_e dct);
int qbman_swp_pull(struct qbman_swp *p, struct qbman_pull_desc *d);
const struct dpaa2_dq *qbman_swp_dqrr_next(struct qbman_swp *s);
void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct dpaa2_dq *dq);
int qbman_result_has_new_result(struct qbman_swp *p, const struct dpaa2_dq *dq);
void qbman_eq_desc_clear(struct qbman_eq_desc *d);
void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success);
void qbman_eq_desc_set_token(struct qbman_eq_desc *d, u8 token);
void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, u32 fqid);
void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, u32 qdid,
u32 qd_bin, u32 qd_prio);
int qbman_swp_enqueue(struct qbman_swp *p, const struct qbman_eq_desc *d,
const struct dpaa2_fd *fd);
void qbman_release_desc_clear(struct qbman_release_desc *d);
void qbman_release_desc_set_bpid(struct qbman_release_desc *d, u16 bpid);
void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable);
int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
const u64 *buffers, unsigned int num_buffers);
int qbman_swp_acquire(struct qbman_swp *s, u16 bpid, u64 *buffers,
unsigned int num_buffers);
int qbman_swp_alt_fq_state(struct qbman_swp *s, u32 fqid,
u8 alt_fq_verb);
int qbman_swp_CDAN_set(struct qbman_swp *s, u16 channelid,
u8 we_mask, u8 cdan_en,
u64 ctx);
void *qbman_swp_mc_start(struct qbman_swp *p);
void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, u8 cmd_verb);
void *qbman_swp_mc_result(struct qbman_swp *p);
/**
* qbman_result_is_DQ() - check if the dequeue result is a dequeue response
* @dq: the dequeue result to be checked
*
* DQRR entries may contain non-dequeue results, ie. notifications
*/
static inline int qbman_result_is_DQ(const struct dpaa2_dq *dq)
{
return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_DQ);
}
/**
* qbman_result_is_SCN() - Check the dequeue result is notification or not
* @dq: the dequeue result to be checked
*
*/
static inline int qbman_result_is_SCN(const struct dpaa2_dq *dq)
{
return !qbman_result_is_DQ(dq);
}
/* FQ Data Availability */
static inline int qbman_result_is_FQDAN(const struct dpaa2_dq *dq)
{
return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQDAN);
}
/* Channel Data Availability */
static inline int qbman_result_is_CDAN(const struct dpaa2_dq *dq)
{
return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_CDAN);
}
/* Congestion State Change */
static inline int qbman_result_is_CSCN(const struct dpaa2_dq *dq)
{
return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_CSCN_WQ);
}
/* Buffer Pool State Change */
static inline int qbman_result_is_BPSCN(const struct dpaa2_dq *dq)
{
return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_BPSCN);
}
/* Congestion Group Count Update */
static inline int qbman_result_is_CGCU(const struct dpaa2_dq *dq)
{
return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_CGCU);
}
/* Retirement */
static inline int qbman_result_is_FQRN(const struct dpaa2_dq *dq)
{
return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQRN);
}
/* Retirement Immediate */
static inline int qbman_result_is_FQRNI(const struct dpaa2_dq *dq)
{
return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQRNI);
}
/* Park */
static inline int qbman_result_is_FQPN(const struct dpaa2_dq *dq)
{
return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQPN);
}
/**
* qbman_result_SCN_state() - Get the state field in State-change notification
*/
static inline u8 qbman_result_SCN_state(const struct dpaa2_dq *scn)
{
return scn->scn.state;
}
#define SCN_RID_MASK 0x00FFFFFF
/**
* qbman_result_SCN_rid() - Get the resource id in State-change notification
*/
static inline u32 qbman_result_SCN_rid(const struct dpaa2_dq *scn)
{
return le32_to_cpu(scn->scn.rid_tok) & SCN_RID_MASK;
}
/**
* qbman_result_SCN_ctx() - Get the context data in State-change notification
*/
static inline u64 qbman_result_SCN_ctx(const struct dpaa2_dq *scn)
{
return le64_to_cpu(scn->scn.ctx);
}
/**
* qbman_swp_fq_schedule() - Move the fq to the scheduled state
* @s: the software portal object
* @fqid: the index of frame queue to be scheduled
*
* There are a couple of different ways that a FQ can end up parked state,
* This schedules it.
*
* Return 0 for success, or negative error code for failure.
*/
static inline int qbman_swp_fq_schedule(struct qbman_swp *s, u32 fqid)
{
return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_SCHEDULE);
}
/**
* qbman_swp_fq_force() - Force the FQ to fully scheduled state
* @s: the software portal object
* @fqid: the index of frame queue to be forced
*
* Force eligible will force a tentatively-scheduled FQ to be fully-scheduled
* and thus be available for selection by any channel-dequeuing behaviour (push
* or pull). If the FQ is subsequently "dequeued" from the channel and is still
* empty at the time this happens, the resulting dq_entry will have no FD.
* (qbman_result_DQ_fd() will return NULL.)
*
* Return 0 for success, or negative error code for failure.
*/
static inline int qbman_swp_fq_force(struct qbman_swp *s, u32 fqid)
{
return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_FORCE);
}
/**
* qbman_swp_fq_xon() - sets FQ flow-control to XON
* @s: the software portal object
* @fqid: the index of frame queue
*
* This setting doesn't affect enqueues to the FQ, just dequeues.
*
* Return 0 for success, or negative error code for failure.
*/
static inline int qbman_swp_fq_xon(struct qbman_swp *s, u32 fqid)
{
return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XON);
}
/**
* qbman_swp_fq_xoff() - sets FQ flow-control to XOFF
* @s: the software portal object
* @fqid: the index of frame queue
*
* This setting doesn't affect enqueues to the FQ, just dequeues.
* XOFF FQs will remain in the tenatively-scheduled state, even when
* non-empty, meaning they won't be selected for scheduled dequeuing.
* If a FQ is changed to XOFF after it had already become truly-scheduled
* to a channel, and a pull dequeue of that channel occurs that selects
* that FQ for dequeuing, then the resulting dq_entry will have no FD.
* (qbman_result_DQ_fd() will return NULL.)
*
* Return 0 for success, or negative error code for failure.
*/
static inline int qbman_swp_fq_xoff(struct qbman_swp *s, u32 fqid)
{
return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XOFF);
}
/* If the user has been allocated a channel object that is going to generate
* CDANs to another channel, then the qbman_swp_CDAN* functions will be
* necessary.
*
* CDAN-enabled channels only generate a single CDAN notification, after which
* they need to be reenabled before they'll generate another. The idea is
* that pull dequeuing will occur in reaction to the CDAN, followed by a
* reenable step. Each function generates a distinct command to hardware, so a
* combination function is provided if the user wishes to modify the "context"
* (which shows up in each CDAN message) each time they reenable, as a single
* command to hardware.
*/
/**
* qbman_swp_CDAN_set_context() - Set CDAN context
* @s: the software portal object
* @channelid: the channel index
* @ctx: the context to be set in CDAN
*
* Return 0 for success, or negative error code for failure.
*/
static inline int qbman_swp_CDAN_set_context(struct qbman_swp *s, u16 channelid,
u64 ctx)
{
return qbman_swp_CDAN_set(s, channelid,
CODE_CDAN_WE_CTX,
0, ctx);
}
/**
* qbman_swp_CDAN_enable() - Enable CDAN for the channel
* @s: the software portal object
* @channelid: the index of the channel to generate CDAN
*
* Return 0 for success, or negative error code for failure.
*/
static inline int qbman_swp_CDAN_enable(struct qbman_swp *s, u16 channelid)
{
return qbman_swp_CDAN_set(s, channelid,
CODE_CDAN_WE_EN,
1, 0);
}
/**
* qbman_swp_CDAN_disable() - disable CDAN for the channel
* @s: the software portal object
* @channelid: the index of the channel to generate CDAN
*
* Return 0 for success, or negative error code for failure.
*/
static inline int qbman_swp_CDAN_disable(struct qbman_swp *s, u16 channelid)
{
return qbman_swp_CDAN_set(s, channelid,
CODE_CDAN_WE_EN,
0, 0);
}
/**
* qbman_swp_CDAN_set_context_enable() - Set CDAN contest and enable CDAN
* @s: the software portal object
* @channelid: the index of the channel to generate CDAN
* @ctx:i the context set in CDAN
*
* Return 0 for success, or negative error code for failure.
*/
static inline int qbman_swp_CDAN_set_context_enable(struct qbman_swp *s,
u16 channelid,
u64 ctx)
{
return qbman_swp_CDAN_set(s, channelid,
CODE_CDAN_WE_EN | CODE_CDAN_WE_CTX,
1, ctx);
}
/* Wraps up submit + poll-for-result */
static inline void *qbman_swp_mc_complete(struct qbman_swp *swp, void *cmd,
u8 cmd_verb)
{
int loopvar = 1000;
qbman_swp_mc_submit(swp, cmd, cmd_verb);
do {
cmd = qbman_swp_mc_result(swp);
} while (!cmd && loopvar--);
WARN_ON(!loopvar);
return cmd;
}
#endif /* __FSL_QBMAN_PORTAL_H */

2
drivers/soc/fsl/qbman/Kconfig
View file

@ -1,5 +1,5 @@
menuconfig FSL_DPAA
bool "Freescale DPAA 1.x support"
bool "QorIQ DPAA1 framework support"
depends on (FSL_SOC_BOOKE || ARCH_LAYERSCAPE)
select GENERIC_ALLOCATOR
help

2
drivers/soc/fsl/qe/Kconfig
View file

@ -3,7 +3,7 @@
#
config QUICC_ENGINE
bool "Freescale QUICC Engine (QE) Support"
bool "QUICC Engine (QE) framework support"
depends on FSL_SOC && PPC32
select GENERIC_ALLOCATOR
select CRC32

28
drivers/soc/fsl/qe/gpio.c
View file

@ -83,6 +83,33 @@ static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
spin_unlock_irqrestore(&qe_gc->lock, flags);
}
static void qe_gpio_set_multiple(struct gpio_chip *gc,
unsigned long *mask, unsigned long *bits)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
struct qe_pio_regs __iomem *regs = mm_gc->regs;
unsigned long flags;
int i;
spin_lock_irqsave(&qe_gc->lock, flags);
for (i = 0; i < gc->ngpio; i++) {
if (*mask == 0)
break;
if (__test_and_clear_bit(i, mask)) {
if (test_bit(i, bits))
qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i));
else
qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i));
}
}
out_be32(&regs->cpdata, qe_gc->cpdata);
spin_unlock_irqrestore(&qe_gc->lock, flags);
}
static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
@ -298,6 +325,7 @@ static int __init qe_add_gpiochips(void)
gc->direction_output = qe_gpio_dir_out;
gc->get = qe_gpio_get;
gc->set = qe_gpio_set;
gc->set_multiple = qe_gpio_set_multiple;
ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
if (ret)

18
drivers/soc/imx/gpc.c
View file

@ -54,7 +54,6 @@ struct imx_pm_domain {
unsigned int reg_offs;
signed char cntr_pdn_bit;
unsigned int ipg_rate_mhz;
unsigned int flags;
};
static inline struct imx_pm_domain *
@ -69,9 +68,6 @@ static int imx6_pm_domain_power_off(struct generic_pm_domain *genpd)
int iso, iso2sw;
u32 val;
if (pd->flags & PGC_DOMAIN_FLAG_NO_PD)
return -EBUSY;
/* Read ISO and ISO2SW power down delays */
regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val);
iso = val & 0x3f;
@ -295,26 +291,31 @@ static struct imx_pm_domain imx_gpc_domains[] = {
struct imx_gpc_dt_data {
int num_domains;
bool err009619_present;
bool err006287_present;
};
static const struct imx_gpc_dt_data imx6q_dt_data = {
.num_domains = 2,
.err009619_present = false,
.err006287_present = false,
};
static const struct imx_gpc_dt_data imx6qp_dt_data = {
.num_domains = 2,
.err009619_present = true,
.err006287_present = false,
};
static const struct imx_gpc_dt_data imx6sl_dt_data = {
.num_domains = 3,
.err009619_present = false,
.err006287_present = true,
};
static const struct imx_gpc_dt_data imx6sx_dt_data = {
.num_domains = 4,
.err009619_present = false,
.err006287_present = false,
};
static const struct of_device_id imx_gpc_dt_ids[] = {
@ -434,8 +435,13 @@ static int imx_gpc_probe(struct platform_device *pdev)
/* Disable PU power down in normal operation if ERR009619 is present */
if (of_id_data->err009619_present)
imx_gpc_domains[GPC_PGC_DOMAIN_PU].flags |=
PGC_DOMAIN_FLAG_NO_PD;
imx_gpc_domains[GPC_PGC_DOMAIN_PU].base.flags |=
GENPD_FLAG_ALWAYS_ON;
/* Keep DISP always on if ERR006287 is present */
if (of_id_data->err006287_present)
imx_gpc_domains[GPC_PGC_DOMAIN_DISPLAY].base.flags |=
GENPD_FLAG_ALWAYS_ON;
if (!pgc_node) {
ret = imx_gpc_old_dt_init(&pdev->dev, regmap,

81
drivers/soc/mediatek/mtk-pmic-wrap.c
View file

@ -146,6 +146,21 @@ static const u32 mt6397_regs[] = {
[PWRAP_DEW_CIPHER_SWRST] = 0xbc24,
};
static const u32 mt6351_regs[] = {
[PWRAP_DEW_DIO_EN] = 0x02F2,
[PWRAP_DEW_READ_TEST] = 0x02F4,
[PWRAP_DEW_WRITE_TEST] = 0x02F6,
[PWRAP_DEW_CRC_EN] = 0x02FA,
[PWRAP_DEW_CRC_VAL] = 0x02FC,
[PWRAP_DEW_CIPHER_KEY_SEL] = 0x0300,
[PWRAP_DEW_CIPHER_IV_SEL] = 0x0302,
[PWRAP_DEW_CIPHER_EN] = 0x0304,
[PWRAP_DEW_CIPHER_RDY] = 0x0306,
[PWRAP_DEW_CIPHER_MODE] = 0x0308,
[PWRAP_DEW_CIPHER_SWRST] = 0x030A,
[PWRAP_DEW_RDDMY_NO] = 0x030C,
};
enum pwrap_regs {
PWRAP_MUX_SEL,
PWRAP_WRAP_EN,
@ -366,6 +381,39 @@ static int mt2701_regs[] = {
[PWRAP_ADC_RDATA_ADDR2] = 0x154,
};
static int mt6797_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
[PWRAP_DIO_EN] = 0x8,
[PWRAP_SIDLY] = 0xC,
[PWRAP_RDDMY] = 0x10,
[PWRAP_CSHEXT_WRITE] = 0x18,
[PWRAP_CSHEXT_READ] = 0x1C,
[PWRAP_CSLEXT_START] = 0x20,
[PWRAP_CSLEXT_END] = 0x24,
[PWRAP_STAUPD_PRD] = 0x28,
[PWRAP_HARB_HPRIO] = 0x50,
[PWRAP_HIPRIO_ARB_EN] = 0x54,
[PWRAP_MAN_EN] = 0x60,
[PWRAP_MAN_CMD] = 0x64,
[PWRAP_WACS0_EN] = 0x70,
[PWRAP_WACS1_EN] = 0x84,
[PWRAP_WACS2_EN] = 0x98,
[PWRAP_INIT_DONE2] = 0x9C,
[PWRAP_WACS2_CMD] = 0xA0,
[PWRAP_WACS2_RDATA] = 0xA4,
[PWRAP_WACS2_VLDCLR] = 0xA8,
[PWRAP_INT_EN] = 0xC0,
[PWRAP_INT_FLG_RAW] = 0xC4,
[PWRAP_INT_FLG] = 0xC8,
[PWRAP_INT_CLR] = 0xCC,
[PWRAP_TIMER_EN] = 0xF4,
[PWRAP_WDT_UNIT] = 0xFC,
[PWRAP_WDT_SRC_EN] = 0x100,
[PWRAP_DCM_EN] = 0x1CC,
[PWRAP_DCM_DBC_PRD] = 0x1D4,
};
static int mt7622_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
@ -635,12 +683,14 @@ static int mt8135_regs[] = {
enum pmic_type {
PMIC_MT6323,
PMIC_MT6351,
PMIC_MT6380,
PMIC_MT6397,
};
enum pwrap_type {
PWRAP_MT2701,
PWRAP_MT6797,
PWRAP_MT7622,
PWRAP_MT8135,
PWRAP_MT8173,
@ -1067,6 +1117,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
break;
case PWRAP_MT2701:
case PWRAP_MT6797:
case PWRAP_MT8173:
pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
break;
@ -1080,8 +1131,6 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 0x1);
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START], 0x1);
switch (wrp->slave->type) {
case PMIC_MT6397:
@ -1091,6 +1140,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
0x1);
break;
case PMIC_MT6323:
case PMIC_MT6351:
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
0x1);
break;
@ -1367,6 +1417,15 @@ static const struct pwrap_slv_type pmic_mt6397 = {
.pwrap_write = pwrap_write16,
};
static const struct pwrap_slv_type pmic_mt6351 = {
.dew_regs = mt6351_regs,
.type = PMIC_MT6351,
.regmap = &pwrap_regmap_config16,
.caps = 0,
.pwrap_read = pwrap_read16,
.pwrap_write = pwrap_write16,
};
static const struct of_device_id of_slave_match_tbl[] = {
{
.compatible = "mediatek,mt6323",
@ -1380,6 +1439,9 @@ static const struct of_device_id of_slave_match_tbl[] = {
}, {
.compatible = "mediatek,mt6397",
.data = &pmic_mt6397,
}, {
.compatible = "mediatek,mt6351",
.data = &pmic_mt6351,
}, {
/* sentinel */
}
@ -1398,6 +1460,18 @@ static const struct pmic_wrapper_type pwrap_mt2701 = {
.init_soc_specific = pwrap_mt2701_init_soc_specific,
};
static const struct pmic_wrapper_type pwrap_mt6797 = {
.regs = mt6797_regs,
.type = PWRAP_MT6797,
.arb_en_all = 0x01fff,
.int_en_all = 0xffffffc6,
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
.has_bridge = 0,
.init_reg_clock = pwrap_common_init_reg_clock,
.init_soc_specific = NULL,
};
static const struct pmic_wrapper_type pwrap_mt7622 = {
.regs = mt7622_regs,
.type = PWRAP_MT7622,
@ -1438,6 +1512,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
{
.compatible = "mediatek,mt2701-pwrap",
.data = &pwrap_mt2701,
}, {
.compatible = "mediatek,mt6797-pwrap",
.data = &pwrap_mt6797,
}, {
.compatible = "mediatek,mt7622-pwrap",
.data = &pwrap_mt7622,

87
drivers/soc/sunxi/sunxi_sram.c
View file

@ -17,6 +17,7 @@
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/soc/sunxi/sunxi_sram.h>
@ -63,6 +64,12 @@ static struct sunxi_sram_desc sun4i_a10_sram_a3_a4 = {
SUNXI_SRAM_MAP(1, 1, "emac")),
};
static struct sunxi_sram_desc sun4i_a10_sram_c1 = {
.data = SUNXI_SRAM_DATA("C1", 0x0, 0x0, 31,
SUNXI_SRAM_MAP(0, 0, "cpu"),
SUNXI_SRAM_MAP(0x7fffffff, 1, "ve")),
};
static struct sunxi_sram_desc sun4i_a10_sram_d = {
.data = SUNXI_SRAM_DATA("D", 0x4, 0x0, 1,
SUNXI_SRAM_MAP(0, 0, "cpu"),
@ -80,6 +87,10 @@ static const struct of_device_id sunxi_sram_dt_ids[] = {
.compatible = "allwinner,sun4i-a10-sram-a3-a4",
.data = &sun4i_a10_sram_a3_a4.data,
},
{
.compatible = "allwinner,sun4i-a10-sram-c1",
.data = &sun4i_a10_sram_c1.data,
},
{
.compatible = "allwinner,sun4i-a10-sram-d",
.data = &sun4i_a10_sram_d.data,
@ -281,13 +292,51 @@ int sunxi_sram_release(struct device *dev)
}
EXPORT_SYMBOL(sunxi_sram_release);
struct sunxi_sramc_variant {
bool has_emac_clock;
};
static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
/* Nothing special */
};
static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = {
.has_emac_clock = true,
};
#define SUNXI_SRAM_EMAC_CLOCK_REG 0x30
static bool sunxi_sram_regmap_accessible_reg(struct device *dev,
unsigned int reg)
{
if (reg == SUNXI_SRAM_EMAC_CLOCK_REG)
return true;
return false;
}
static struct regmap_config sunxi_sram_emac_clock_regmap = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
/* last defined register */
.max_register = SUNXI_SRAM_EMAC_CLOCK_REG,
/* other devices have no business accessing other registers */
.readable_reg = sunxi_sram_regmap_accessible_reg,
.writeable_reg = sunxi_sram_regmap_accessible_reg,
};
static int sunxi_sram_probe(struct platform_device *pdev)
{
struct resource *res;
struct dentry *d;
struct regmap *emac_clock;
const struct sunxi_sramc_variant *variant;
sram_dev = &pdev->dev;
variant = of_device_get_match_data(&pdev->dev);
if (!variant)
return -EINVAL;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base))
@ -300,12 +349,46 @@ static int sunxi_sram_probe(struct platform_device *pdev)
if (!d)
return -ENOMEM;
if (variant->has_emac_clock) {
emac_clock = devm_regmap_init_mmio(&pdev->dev, base,
&sunxi_sram_emac_clock_regmap);
if (IS_ERR(emac_clock))
return PTR_ERR(emac_clock);
}
return 0;
}
static const struct of_device_id sunxi_sram_dt_match[] = {
{ .compatible = "allwinner,sun4i-a10-sram-controller" },
{ .compatible = "allwinner,sun50i-a64-sram-controller" },
{
.compatible = "allwinner,sun4i-a10-sram-controller",
.data = &sun4i_a10_sramc_variant,
},
{
.compatible = "allwinner,sun4i-a10-system-control",
.data = &sun4i_a10_sramc_variant,
},
{
.compatible = "allwinner,sun5i-a13-system-control",
.data = &sun4i_a10_sramc_variant,
},
{
.compatible = "allwinner,sun8i-a23-system-control",
.data = &sun4i_a10_sramc_variant,
},
{
.compatible = "allwinner,sun8i-h3-system-control",
.data = &sun4i_a10_sramc_variant,
},
{
.compatible = "allwinner,sun50i-a64-sram-controller",
.data = &sun50i_a64_sramc_variant,
},
{
.compatible = "allwinner,sun50i-a64-system-control",
.data = &sun50i_a64_sramc_variant,
},
{ },
};
MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);

76
drivers/soc/ti/wkup_m3_ipc.c
View file

@ -46,6 +46,7 @@
#define M3_BASELINE_VERSION 0x191
#define M3_STATUS_RESP_MASK (0xffff << 16)
#define M3_FW_VERSION_MASK 0xffff
#define M3_WAKE_SRC_MASK 0xff
#define M3_STATE_UNKNOWN 0
#define M3_STATE_RESET 1
@ -55,6 +56,23 @@
static struct wkup_m3_ipc *m3_ipc_state;
static const struct wkup_m3_wakeup_src wakeups[] = {
{.irq_nr = 35, .src = "USB0_PHY"},
{.irq_nr = 36, .src = "USB1_PHY"},
{.irq_nr = 40, .src = "I2C0"},
{.irq_nr = 41, .src = "RTC Timer"},
{.irq_nr = 42, .src = "RTC Alarm"},
{.irq_nr = 43, .src = "Timer0"},
{.irq_nr = 44, .src = "Timer1"},
{.irq_nr = 45, .src = "UART"},
{.irq_nr = 46, .src = "GPIO0"},
{.irq_nr = 48, .src = "MPU_WAKE"},
{.irq_nr = 49, .src = "WDT0"},
{.irq_nr = 50, .src = "WDT1"},
{.irq_nr = 51, .src = "ADC_TSC"},
{.irq_nr = 0, .src = "Unknown"},
};
static void am33xx_txev_eoi(struct wkup_m3_ipc *m3_ipc)
{
writel(AM33XX_M3_TXEV_ACK,
@ -329,12 +347,45 @@ static int wkup_m3_finish_low_power(struct wkup_m3_ipc *m3_ipc)
return 0;
}
/**
* wkup_m3_request_wake_src - Get the wakeup source info passed from wkup_m3
* @m3_ipc: Pointer to wkup_m3_ipc context
*/
static const char *wkup_m3_request_wake_src(struct wkup_m3_ipc *m3_ipc)
{
unsigned int wakeup_src_idx;
int j, val;
val = wkup_m3_ctrl_ipc_read(m3_ipc, 6);
wakeup_src_idx = val & M3_WAKE_SRC_MASK;
for (j = 0; j < ARRAY_SIZE(wakeups) - 1; j++) {
if (wakeups[j].irq_nr == wakeup_src_idx)
return wakeups[j].src;
}
return wakeups[j].src;
}
/**
* wkup_m3_set_rtc_only - Set the rtc_only flag
* @wkup_m3_wakeup: struct wkup_m3_wakeup_src * gets assigned the
* wakeup src value
*/
static void wkup_m3_set_rtc_only(struct wkup_m3_ipc *m3_ipc)
{
if (m3_ipc_state)
m3_ipc_state->is_rtc_only = true;
}
static struct wkup_m3_ipc_ops ipc_ops = {
.set_mem_type = wkup_m3_set_mem_type,
.set_resume_address = wkup_m3_set_resume_address,
.prepare_low_power = wkup_m3_prepare_low_power,
.finish_low_power = wkup_m3_finish_low_power,
.request_pm_status = wkup_m3_request_pm_status,
.request_wake_src = wkup_m3_request_wake_src,
.set_rtc_only = wkup_m3_set_rtc_only,
};
/**
@ -484,6 +535,30 @@ static int wkup_m3_ipc_remove(struct platform_device *pdev)
return 0;
}
static int __maybe_unused wkup_m3_ipc_suspend(struct device *dev)
{
/*
* Nothing needs to be done on suspend even with rtc_only flag set
*/
return 0;
}
static int __maybe_unused wkup_m3_ipc_resume(struct device *dev)
{
if (m3_ipc_state->is_rtc_only) {
rproc_shutdown(m3_ipc_state->rproc);
rproc_boot(m3_ipc_state->rproc);
}
m3_ipc_state->is_rtc_only = false;
return 0;
}
static const struct dev_pm_ops wkup_m3_ipc_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(wkup_m3_ipc_suspend, wkup_m3_ipc_resume)
};
static const struct of_device_id wkup_m3_ipc_of_match[] = {
{ .compatible = "ti,am3352-wkup-m3-ipc", },
{ .compatible = "ti,am4372-wkup-m3-ipc", },
@ -497,6 +572,7 @@ static struct platform_driver wkup_m3_ipc_driver = {
.driver = {
.name = "wkup_m3_ipc",
.of_match_table = wkup_m3_ipc_of_match,
.pm = &wkup_m3_ipc_pm_ops,
},
};