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ARM: SoC driver updates
Some of the larger changes this merge window:
- Removal of drivers for Exynos5440, a Samsung SoC that never saw
widespread use.
- Uniphier support for USB3 and SPI reset handling
- Syste control and SRAM drivers and bindings for Allwinner platforms
- Qualcomm AOSS (Always-on subsystem) reset controller drivers
- Raspberry Pi hwmon driver for voltage
- Mediatek pwrap (pmic) support for MT6797 SoC
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson:
"Some of the larger changes this merge window:
- Removal of drivers for Exynos5440, a Samsung SoC that never saw
widespread use.
- Uniphier support for USB3 and SPI reset handling
- Syste control and SRAM drivers and bindings for Allwinner platforms
- Qualcomm AOSS (Always-on subsystem) reset controller drivers
- Raspberry Pi hwmon driver for voltage
- Mediatek pwrap (pmic) support for MT6797 SoC"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (52 commits)
drivers/firmware: psci_checker: stash and use topology_core_cpumask for hotplug tests
soc: fsl: cleanup Kconfig menu
soc: fsl: dpio: Convert DPIO documentation to .rst
staging: fsl-mc: Remove remaining files
staging: fsl-mc: Move DPIO from staging to drivers/soc/fsl
staging: fsl-dpaa2: eth: move generic FD defines to DPIO
soc: fsl: qe: gpio: Add qe_gpio_set_multiple
usb: host: exynos: Remove support for Exynos5440
clk: samsung: Remove support for Exynos5440
soc: sunxi: Add the A13, A23 and H3 system control compatibles
reset: uniphier: add reset control support for SPI
cpufreq: exynos: Remove support for Exynos5440
ata: ahci-platform: Remove support for Exynos5440
soc: imx6qp: Use GENPD_FLAG_ALWAYS_ON for PU errata
soc: mediatek: pwrap: add mt6351 driver for mt6797 SoCs
soc: mediatek: pwrap: add pwrap driver for mt6797 SoCs
soc: mediatek: pwrap: fix cipher init setting error
dt-bindings: pwrap: mediatek: add pwrap support for MT6797
reset: uniphier: add USB3 core reset control
dt-bindings: reset: uniphier: add USB3 core reset support
...
This commit is contained in:
Linus Torvalds
commit
f3ea496213
82 changed files with 1360 additions and 880 deletions
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@ -15,6 +15,8 @@
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/* SmartReflex sysc found on 36xx and later */
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#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26)
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#define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4)
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/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */
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#define SYSC_IDLE_FORCE 0
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#define SYSC_IDLE_NO 1
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@ -168,5 +168,6 @@
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#define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
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#define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
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#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
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#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
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#endif
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@ -1,44 +0,0 @@
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/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Author: Andrzej Hajda <a.hajda@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Device Tree binding constants for Exynos5440 clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5440_H
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#define _DT_BINDINGS_CLOCK_EXYNOS_5440_H
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#define CLK_XTAL 1
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#define CLK_ARM_CLK 2
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#define CLK_CPLLA 3
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#define CLK_CPLLB 4
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#define CLK_SPI_BAUD 16
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#define CLK_PB0_250 17
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#define CLK_PR0_250 18
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#define CLK_PR1_250 19
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#define CLK_B_250 20
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#define CLK_B_125 21
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#define CLK_B_200 22
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#define CLK_SATA 23
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#define CLK_USB 24
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#define CLK_GMAC0 25
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#define CLK_CS250 26
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#define CLK_PB0_250_O 27
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#define CLK_PR0_250_O 28
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#define CLK_PR1_250_O 29
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#define CLK_B_250_O 30
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#define CLK_B_125_O 31
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#define CLK_B_200_O 32
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#define CLK_SATA_O 33
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#define CLK_USB_O 34
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#define CLK_GMAC0_O 35
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#define CLK_CS250_O 36
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/* must be greater than maximal clock id */
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#define CLK_NR_CLKS 37
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5440_H */
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17
include/dt-bindings/reset/qcom,sdm845-aoss.h
Normal file
17
include/dt-bindings/reset/qcom,sdm845-aoss.h
Normal file
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@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
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#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
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#define AOSS_CC_MSS_RESTART 0
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#define AOSS_CC_CAMSS_RESTART 1
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#define AOSS_CC_VENUS_RESTART 2
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#define AOSS_CC_GPU_RESTART 3
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#define AOSS_CC_DISPSS_RESTART 4
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#define AOSS_CC_WCSS_RESTART 5
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#define AOSS_CC_LPASS_RESTART 6
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#endif
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