From dd51641fbd67c90e726064270ad20bde606a67be Mon Sep 17 00:00:00 2001
From: Veera Vegivada <vvegivad@qti.qualcomm.com>
Date: Thu, 17 Dec 2020 14:28:23 +0530
Subject: [PATCH 1/2] ARM: dts: msm: Add cpufreq HW device node SDMSHRIKE

Add cpufreq HW device node to scale 4 domain-0 & 4 domain-1 cores
on SDMSHRIKE SoCs.

Change-Id: I2cf89a059d028ed559623dba0d4abebfc1fe4c85
---
 qcom/sdmshrike.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi
index a5f732365872..fb75c9c7178d 100644
--- a/qcom/sdmshrike.dtsi
+++ b/qcom/sdmshrike.dtsi
@@ -39,6 +39,7 @@
 			capacity-dmips-mhz = <1024>;
 			cache-size = <0x8000>;
 			next-level-cache = <&L2_0>;
+			qcom,freq-domain = <&cpufreq_hw 0 4>;
 			#cooling-cells = <2>;
 			L2_0: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -72,6 +73,7 @@
 			capacity-dmips-mhz = <1024>;
 			cache-size = <0x8000>;
 			next-level-cache = <&L2_1>;
+			qcom,freq-domain = <&cpufreq_hw 0 4>;
 			#cooling-cells = <2>;
 			L2_1: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -99,6 +101,7 @@
 			capacity-dmips-mhz = <1024>;
 			cache-size = <0x8000>;
 			next-level-cache = <&L2_2>;
+			qcom,freq-domain = <&cpufreq_hw 0 4>;
 			#cooling-cells = <2>;
 			L2_2: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -126,6 +129,7 @@
 			capacity-dmips-mhz = <1024>;
 			cache-size = <0x8000>;
 			next-level-cache = <&L2_3>;
+			qcom,freq-domain = <&cpufreq_hw 0 4>;
 			#cooling-cells = <2>;
 			L2_3: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -153,6 +157,7 @@
 			capacity-dmips-mhz = <1740>;
 			cache-size = <0x20000>;
 			next-level-cache = <&L2_4>;
+			qcom,freq-domain = <&cpufreq_hw 1 4>;
 			#cooling-cells = <2>;
 			L2_4: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -180,6 +185,7 @@
 			capacity-dmips-mhz = <1740>;
 			cache-size = <0x20000>;
 			next-level-cache = <&L2_5>;
+			qcom,freq-domain = <&cpufreq_hw 1 4>;
 			#cooling-cells = <2>;
 			L2_5: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -207,6 +213,7 @@
 			capacity-dmips-mhz = <1740>;
 			cache-size = <0x20000>;
 			next-level-cache = <&L2_6>;
+			qcom,freq-domain = <&cpufreq_hw 1 4>;
 			#cooling-cells = <2>;
 			L2_6: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -234,6 +241,7 @@
 			capacity-dmips-mhz = <1740>;
 			cache-size = <0x20000>;
 			next-level-cache = <&L2_7>;
+			qcom,freq-domain = <&cpufreq_hw 1 4>;
 			#cooling-cells = <2>;
 			L2_7: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -948,6 +956,15 @@
 		#clock-cells = <1>;
 	};
 
+	cpufreq_hw: cpufreq@18323000 {
+		compatible = "qcom,cpufreq-hw";
+		reg = <0x18323000 0x1400>, <0x18325800 0x1400>;
+		reg-names = "freq-domain0", "freq-domain1";
+		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+		clock-names = "xo", "alternate";
+		#freq-domain-cells = <2>;
+	};
+
 	tcsr_mutex_block: syscon@1f40000 {
 		compatible = "syscon";
 		reg = <0x1f40000 0x20000>;

From b1ed71a1b017fdf6df9055bd04fce2109f2fe5a3 Mon Sep 17 00:00:00 2001
From: Veera Vegivada <vvegivad@qti.qualcomm.com>
Date: Tue, 1 Dec 2020 13:39:23 +0530
Subject: [PATCH 2/2] ARM: dts: msm: Enable L3 interconnect driver for scshrike

Enable L3 interconnect driver so that consumers are
able to obtain their path handles properly.

Change-Id: I99a5085192c1d551e5d0973bb50f96d27d97746a
---
 qcom/sdmshrike.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi
index fb75c9c7178d..57a88936e1df 100644
--- a/qcom/sdmshrike.dtsi
+++ b/qcom/sdmshrike.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/clock/qcom,videocc-sm8150.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/interconnect/qcom,scshrike.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -716,6 +717,14 @@
 		};
 	};
 
+	osm_l3: interconnect@18321000 {
+		reg = <0x18321000 0x1400>;
+		compatible = "qcom,scshrike-osm-l3";
+		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+		clock-names = "xo", "alternate";
+		#interconnect-cells = <1>;
+	};
+
 	config_noc: interconnect@1500000 {
 		reg = <0x1500000 0x7400>;
 		compatible = "qcom,scshrike-config_noc";