From 6b84a80dde1ab6801f606e9f81cea291ef462da7 Mon Sep 17 00:00:00 2001
From: Vivek Pernamitta <vpernami@qti.qualcomm.com>
Date: Wed, 4 Nov 2020 16:05:27 +0530
Subject: [PATCH] ARM: dts: msm: Use PCIe_MSI for Shima

This reverts commit a986821e2562b51c88ba1be50ca37edec93b3c4f.
Commit a986821e2562b5 ("Revert "ARM: dts: msm: Use PCIe_MSI
for Shima"") reverted the MSI changes due to there
are pending MSI interrupts in PCIe DRV suspend state from
device, which caused NOC error when host try to read MSI
status register. Re-enabled the MSI changes as there
is an changes made in ADSP side to check any pending
interrupts before entering L1SS sleep.

Change-Id: I6faa18002395d3b100e12362446da96ddb5b29ee
---
 qcom/shima-pcie.dtsi | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi
index 32573d6def76..fbe74ebfb44d 100644
--- a/qcom/shima-pcie.dtsi
+++ b/qcom/shima-pcie.dtsi
@@ -33,7 +33,7 @@
 				0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
 				0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 
-		msi-parent = <&pcie0_msi>;
+		msi-parent = <&pcie0_msi_snps>;
 
 		perst-gpio = <&tlmm 94 0>;
 		wake-gpio = <&tlmm 96 0>;
@@ -194,6 +194,15 @@
 		};
 	};
 
+	pcie0_msi_snps: qcom,pcie0_msi@a0000000 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0xa0000000 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,snps;
+	};
+
 	pcie0_msi: qcom,pcie0_msi@17a10040 {
 		compatible = "qcom,pci-msi";
 		msi-controller;