From f48391025ede5a676a047e0bef425fc71ac72f65 Mon Sep 17 00:00:00 2001 From: Himateja Reddy Date: Wed, 18 Mar 2020 12:45:36 -0700 Subject: [PATCH] ARM: dts: msm: add 4 new compute DSP context banks for lahaina Add 4 new compute DSP context banks for lahaina, in addition to the existing 8 context banks, so that 12 concurrent fastrpc sessions can be run on the remote subsystem. Change-Id: Id3117510972d002e0d345157295dec9d271b2de7 Acked-by: Thyagarajan Venkatanarayanan --- qcom/lahaina.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 03580c92d14e..2aa82bed299a 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -2008,6 +2008,46 @@ shared-cb = <4>; dma-coherent; }; + + qcom,msm_fastrpc_compute_cb16 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x118B 0x0420>, + <&apps_smmu 0x216B 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb17 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x118C 0x0420>, + <&apps_smmu 0x216C 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb18 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x118D 0x0420>, + <&apps_smmu 0x216D 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb19 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x118E 0x0420>, + <&apps_smmu 0x216E 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent; + }; }; llcc_pmu: llcc-pmu@9095000 {