From 9d53b47d4ea10ab1cdcfec5237b413a6ae0539ee Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Thu, 22 Dec 2022 19:02:46 +0530 Subject: [PATCH] disp: msm: sde: program read pointer after configuring vsync_counter_en Program the read pointer after configuring the tearcheck registers. The read pointer register should be configured after VSYNC_COUNTER_EN is set as per hw programming sequence. Change-Id: I2fa1429798fab51d08091e74a33f1b1c4382eafe Signed-off-by: Veera Sundaram Sankaran Signed-off-by: Akash Gajjar (cherry picked from commit fce2fc595f1a9881255faa651e8d1b9e43cbf906) --- msm/sde/sde_hw_intf.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/msm/sde/sde_hw_intf.c b/msm/sde/sde_hw_intf.c index 925db925364a..83b3971427d8 100644 --- a/msm/sde/sde_hw_intf.c +++ b/msm/sde/sde_hw_intf.c @@ -565,8 +565,6 @@ static int sde_hw_intf_setup_te_config(struct sde_hw_intf *intf, * less than 2^16 vsync clk cycles. */ spin_lock(&tearcheck_spinlock); - SDE_REG_WRITE(c, INTF_TEAR_SYNC_WRCOUNT, - (te->start_pos + te->sync_threshold_start + 1)); SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg); wmb(); /* disable vsync counter before updating single buffer registers */ SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_HEIGHT, te->sync_cfg_height); @@ -579,6 +577,10 @@ static int sde_hw_intf_setup_te_config(struct sde_hw_intf *intf, te->sync_threshold_start)); cfg |= BIT(19); /* VSYNC_COUNTER_EN */ SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg); + wmb(); /* ensure vsync_counter_en is written */ + + SDE_REG_WRITE(c, INTF_TEAR_SYNC_WRCOUNT, + (te->start_pos + te->sync_threshold_start + 1)); spin_unlock(&tearcheck_spinlock); return 0;