From e30daed76f696edd2d834414b04dbfb0b8fe4b15 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 26 Oct 2020 15:27:56 -0700 Subject: [PATCH 1/3] dt-bindings: arm: msm: add MX entries for PCIe There are chipsets which require explicit votes for MX rails and its corners based on PCIe Gen speed. Add a entries for MX in DT so PCIe bus driver can properly vote and scale corners for MX. Change-Id: Ib7891ab528594f4f8a81568daafbe6297fcb60be --- bindings/pci/pci-msm.txt | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index 8a9fa1e1c6fe..8d64a0fc0b9c 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -123,6 +123,7 @@ Main node - "vreg-1.8-supply" power supply for PCIe PHY - "vreg-0.9-supply" power supply for PCIe PHY - "vreg-cx-supply" power supply for PCIe core + - "vreg-mx-supply" power supply for PCIe core/PHY - "vreg-3.3-supply" (opt) power supply for PCIe endpoint - qcom,-voltage-level: @@ -134,8 +135,10 @@ Main node - qcom,bw-scale: Usage: optional Value type: - Definition: List of CX voltage corner and rate change clock frequency - pair for each PCIe GEN speed + Definition: Tuple consisting of CX and MX voltage corners, and rate + change clock frequencies for each supported PCIe Gen speed. + ex: + <[min CX voltage] [min MX voltage] [Rate change clk frequency]> interconnect-names: Usage: optional @@ -461,14 +464,30 @@ Example vreg-1.8-supply = <&pm8150l_l3>; vreg-0.9-supply = <&pm8150_l5>; vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; vreg-3.3-supply = <&pm8150_l1>; qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>; qcom,vreg-0.9-voltage-level = <950000 950000 24000>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = ; /* Gen3 */ + qcom,vreg-mx-voltage-level = ; + qcom,bw-scale = /* Gen1 */ + ; interconnect-names = "icc_path"; interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; From 1b25bc86023f9a350250459c5e2d06d859cd5557 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 26 Oct 2020 15:39:06 -0700 Subject: [PATCH 2/3] ARM: dts: msm: add MX entries to qcom,bw-scale for PCIe on lahaina Explicit MX voting and scaling is required for PCIe on some chipsets and there are updates to PCIe bus driver to support this. Although PCIe on lahaina does not need to explicitly vote for MX, updates to lahaina PCIe DT nodes are required to be compatible with the new qcom,bw-scale structure. Therefore, add MX entries to qcom,bw-scale for both PCIe nodes on lahaina. Change-Id: If707f61f78e4d99df118ebbfb516d639e5b4f851 --- qcom/lahaina-pcie.dtsi | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi index 9c106f0bd059..c72e6031377f 100644 --- a/qcom/lahaina-pcie.dtsi +++ b/qcom/lahaina-pcie.dtsi @@ -53,10 +53,18 @@ qcom,vreg-0p9-voltage-level = <880000 880000 47900>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = - ; /* Gen3 */ + qcom,bw-scale = /* Gen1 */ + ; interconnect-names = "icc_path"; interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; @@ -284,10 +292,18 @@ qcom,vreg-0p9-voltage-level = <880000 880000 99000>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = - ; /* Gen3 */ + qcom,bw-scale = /* Gen1 */ + ; interconnect-names = "icc_path"; interconnects = <&aggre2_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>; From 0b88f624d564bdd4bb438265f69d7db7d5ea5049 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 27 Oct 2020 11:25:58 -0700 Subject: [PATCH 3/3] ARM: dts: msm: add MX entries to qcom,bw-scale for PCIe on shima Explicit MX voting and scaling is required for PCIe on some chipsets and there are updates to PCIe bus driver to support this. Although PCIe on shima does not need to explicitly vote for MX, updates to shima PCIe DT node are required to be compatible with the new qcom,bw-scale structure. Therefore, add MX entries to qcom,bw-scale for PCIe on shima. Change-Id: I4b93b92ee8e401c554e17e769432d3c22998ad98 --- qcom/shima-pcie.dtsi | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index 32573d6def76..eb3c0f409669 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -53,10 +53,18 @@ qcom,vreg-0p9-voltage-level = <880000 880000 47900>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = - ; /* Gen3 */ + qcom,bw-scale = /* Gen1 */ + ; interconnect-names = "icc_path"; interconnects = <&aggre1_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;