A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-12 07:37:31 -04:00
Code Issues Projects Releases Packages Wiki Activity

Merge "mmc: sdhci-msm: Update to enhanced SDCC5 DLL power up sequence"

Browse source
This commit is contained in:
qctecmdr 2020-10-26 09:53:32 -07:00 • committed by Gerrit - the friendly Code Review server
commit f4e98f0cf5
1 changed files with 15 additions and 21 deletions
Download patch file Download diff file Expand all files Collapse all files

36
drivers/mmc/host/sdhci-msm.c
View file

@ -129,6 +129,7 @@
#define FINE_TUNE_MODE_EN BIT(27)
#define BIAS_OK_SIGNAL BIT(29)
#define DLL_CONFIG_3_POR_VAL 0x10
#define DLL_CONFIG_POR_VAL 0x6007642C
#define INVALID_TUNING_PHASE -1
@ -891,7 +892,7 @@ static int msm_init_cm_dll(struct sdhci_host *host,
else
ddr_cfg_offset = msm_offset->core_ddr_config_old;
if (msm_host->dll_hsr->ddr_config)
if (msm_host->dll_hsr && msm_host->dll_hsr->ddr_config)
writel_relaxed(msm_host->dll_hsr->ddr_config, host->ioaddr +
ddr_cfg_offset);
else
@ -930,16 +931,14 @@ static int msm_init_cm_dll(struct sdhci_host *host,
udelay(5);
}
/*
* Step 10 - Update the lower two bytes of DLL_CONFIG only with
* HSR values. Since these are the static settings.
*/
if (msm_host->dll_hsr) {
writel_relaxed((readl_relaxed(host->ioaddr +
msm_offset->core_dll_config) |
(msm_host->dll_hsr->dll_config & 0xffff)),
host->ioaddr + msm_offset->core_dll_config);
}
/* Step 10 - Config DLL_CONFIG with HSR values */
if (msm_host->dll_hsr && msm_host->dll_hsr->dll_config)
writel_relaxed(msm_host->dll_hsr->dll_config |
CORE_DLL_RST | CORE_DLL_PDN, host->ioaddr +
msm_offset->core_dll_config);
else
writel_relaxed(DLL_CONFIG_POR_VAL, host->ioaddr +
msm_offset->core_dll_config);
/* Step 11 - Wait for 52us */
spin_unlock_irqrestore(&host->lock, flags);
@ -976,27 +975,22 @@ static int msm_init_cm_dll(struct sdhci_host *host,
msm_offset->core_dll_config_2);
}
/* Step 16 - Set DLL_EN bit to 1. */
writel_relaxed((readl_relaxed(host->ioaddr +
msm_offset->core_dll_config) | CORE_DLL_EN),
host->ioaddr + msm_offset->core_dll_config);
/*
* Step 17 - Wait for 8000 input clock. Here we calculate the
* Step 16 - Wait for 8000 input clock. Here we calculate the
* delay from fixed clock freq 192MHz, which turns out 42us.
*/
spin_unlock_irqrestore(&host->lock, flags);
usleep_range(45, 50);
spin_lock_irqsave(&host->lock, flags);
/* Step 18 - Set CK_OUT_EN bit to 1. */
/* Step 17 - Set CK_OUT_EN bit to 1. */
writel_relaxed((readl_relaxed(host->ioaddr +
msm_offset->core_dll_config)
| CORE_CK_OUT_EN), host->ioaddr +
msm_offset->core_dll_config);
/*
* Step 19 - Wait until DLL_LOCK bit of DLL_STATUS register
* Step 18 - Wait until DLL_LOCK bit of DLL_STATUS register
* becomes '1'.
*/
while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
@ -1014,7 +1008,7 @@ static int msm_init_cm_dll(struct sdhci_host *host,
out:
if (core_vendor_spec & CORE_CLK_PWRSAVE) {
/* Step 20 - Reenable PWRSAVE as needed */
/* Step 19 - Reenable PWRSAVE as needed */
writel_relaxed((readl_relaxed(host->ioaddr +
msm_offset->core_vendor_spec)
| CORE_CLK_PWRSAVE), host->ioaddr +
@ -1274,7 +1268,7 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
else
ddr_cfg_offset = msm_offset->core_ddr_config_old;
if (msm_host->dll_hsr->ddr_config)
if (msm_host->dll_hsr && msm_host->dll_hsr->ddr_config)
config = msm_host->dll_hsr->ddr_config;
else
config = DDR_CONFIG_POR_VAL;