mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 11:41:38 -04:00
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next into for-davem
This commit is contained in:
commit
f5237f278f
249 changed files with 26303 additions and 3190 deletions
|
|
@ -74,6 +74,16 @@ static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned gpio)
|
|||
ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
|
||||
}
|
||||
|
||||
static int ssb_gpio_chipco_to_irq(struct gpio_chip *chip, unsigned gpio)
|
||||
{
|
||||
struct ssb_bus *bus = ssb_gpio_get_bus(chip);
|
||||
|
||||
if (bus->bustype == SSB_BUSTYPE_SSB)
|
||||
return ssb_mips_irq(bus->chipco.dev) + 2;
|
||||
else
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int ssb_gpio_chipco_init(struct ssb_bus *bus)
|
||||
{
|
||||
struct gpio_chip *chip = &bus->gpio;
|
||||
|
|
@ -86,6 +96,7 @@ static int ssb_gpio_chipco_init(struct ssb_bus *bus)
|
|||
chip->set = ssb_gpio_chipco_set_value;
|
||||
chip->direction_input = ssb_gpio_chipco_direction_input;
|
||||
chip->direction_output = ssb_gpio_chipco_direction_output;
|
||||
chip->to_irq = ssb_gpio_chipco_to_irq;
|
||||
chip->ngpio = 16;
|
||||
/* There is just one SoC in one device and its GPIO addresses should be
|
||||
* deterministic to address them more easily. The other buses could get
|
||||
|
|
@ -134,6 +145,16 @@ static int ssb_gpio_extif_direction_output(struct gpio_chip *chip,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int ssb_gpio_extif_to_irq(struct gpio_chip *chip, unsigned gpio)
|
||||
{
|
||||
struct ssb_bus *bus = ssb_gpio_get_bus(chip);
|
||||
|
||||
if (bus->bustype == SSB_BUSTYPE_SSB)
|
||||
return ssb_mips_irq(bus->extif.dev) + 2;
|
||||
else
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int ssb_gpio_extif_init(struct ssb_bus *bus)
|
||||
{
|
||||
struct gpio_chip *chip = &bus->gpio;
|
||||
|
|
@ -144,6 +165,7 @@ static int ssb_gpio_extif_init(struct ssb_bus *bus)
|
|||
chip->set = ssb_gpio_extif_set_value;
|
||||
chip->direction_input = ssb_gpio_extif_direction_input;
|
||||
chip->direction_output = ssb_gpio_extif_direction_output;
|
||||
chip->to_irq = ssb_gpio_extif_to_irq;
|
||||
chip->ngpio = 5;
|
||||
/* There is just one SoC in one device and its GPIO addresses should be
|
||||
* deterministic to address them more easily. The other buses could get
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
|
||||
#include <linux/ssb/ssb.h>
|
||||
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/serial_reg.h>
|
||||
|
|
@ -17,6 +18,25 @@
|
|||
|
||||
#include "ssb_private.h"
|
||||
|
||||
static const char *part_probes[] = { "bcm47xxpart", NULL };
|
||||
|
||||
static struct physmap_flash_data ssb_pflash_data = {
|
||||
.part_probe_types = part_probes,
|
||||
};
|
||||
|
||||
static struct resource ssb_pflash_resource = {
|
||||
.name = "ssb_pflash",
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
struct platform_device ssb_pflash_dev = {
|
||||
.name = "physmap-flash",
|
||||
.dev = {
|
||||
.platform_data = &ssb_pflash_data,
|
||||
},
|
||||
.resource = &ssb_pflash_resource,
|
||||
.num_resources = 1,
|
||||
};
|
||||
|
||||
static inline u32 mips_read32(struct ssb_mipscore *mcore,
|
||||
u16 offset)
|
||||
|
|
@ -189,14 +209,15 @@ static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
|
|||
static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
|
||||
{
|
||||
struct ssb_bus *bus = mcore->dev->bus;
|
||||
struct ssb_pflash *pflash = &mcore->pflash;
|
||||
|
||||
/* When there is no chipcommon on the bus there is 4MB flash */
|
||||
if (!ssb_chipco_available(&bus->chipco)) {
|
||||
mcore->pflash.present = true;
|
||||
mcore->pflash.buswidth = 2;
|
||||
mcore->pflash.window = SSB_FLASH1;
|
||||
mcore->pflash.window_size = SSB_FLASH1_SZ;
|
||||
return;
|
||||
pflash->present = true;
|
||||
pflash->buswidth = 2;
|
||||
pflash->window = SSB_FLASH1;
|
||||
pflash->window_size = SSB_FLASH1_SZ;
|
||||
goto ssb_pflash;
|
||||
}
|
||||
|
||||
/* There is ChipCommon, so use it to read info about flash */
|
||||
|
|
@ -208,16 +229,23 @@ static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
|
|||
break;
|
||||
case SSB_CHIPCO_FLASHT_PARA:
|
||||
pr_debug("Found parallel flash\n");
|
||||
mcore->pflash.present = true;
|
||||
mcore->pflash.window = SSB_FLASH2;
|
||||
mcore->pflash.window_size = SSB_FLASH2_SZ;
|
||||
pflash->present = true;
|
||||
pflash->window = SSB_FLASH2;
|
||||
pflash->window_size = SSB_FLASH2_SZ;
|
||||
if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
|
||||
& SSB_CHIPCO_CFG_DS16) == 0)
|
||||
mcore->pflash.buswidth = 1;
|
||||
pflash->buswidth = 1;
|
||||
else
|
||||
mcore->pflash.buswidth = 2;
|
||||
pflash->buswidth = 2;
|
||||
break;
|
||||
}
|
||||
|
||||
ssb_pflash:
|
||||
if (pflash->present) {
|
||||
ssb_pflash_data.width = pflash->buswidth;
|
||||
ssb_pflash_resource.start = pflash->window;
|
||||
ssb_pflash_resource.end = pflash->window + pflash->window_size;
|
||||
}
|
||||
}
|
||||
|
||||
u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
|
||||
|
|
|
|||
|
|
@ -540,6 +540,14 @@ static int ssb_devices_register(struct ssb_bus *bus)
|
|||
dev_idx++;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SSB_DRIVER_MIPS
|
||||
if (bus->mipscore.pflash.present) {
|
||||
err = platform_device_register(&ssb_pflash_dev);
|
||||
if (err)
|
||||
pr_err("Error registering parallel flash\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
error:
|
||||
/* Unwind the already registered devices. */
|
||||
|
|
|
|||
|
|
@ -228,6 +228,10 @@ static inline int ssb_sflash_init(struct ssb_chipcommon *cc)
|
|||
}
|
||||
#endif /* CONFIG_SSB_SFLASH */
|
||||
|
||||
#ifdef CONFIG_SSB_DRIVER_MIPS
|
||||
extern struct platform_device ssb_pflash_dev;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SSB_DRIVER_EXTIF
|
||||
extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
|
||||
extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
|
||||
|
|
|
|||
Loading…
Reference in a new issue