From f549366d31cf44455f601e90dd9bc5cb78905a8a Mon Sep 17 00:00:00 2001 From: Madhuri Medasani Date: Fri, 26 Mar 2021 19:19:51 +0530 Subject: [PATCH] dt-bindings: clock: Add support for BLAIR clock controllers Update the GCC, GPUCC and DISPCC bindings for BLAIR device. Change-Id: Icd841e4182dad6f0150a809a965cb82c94ddd26c --- bindings/clock/qcom,dispcc.txt | 1 + bindings/clock/qcom,gcc.txt | 1 + bindings/clock/qcom,gpucc.txt | 1 + 3 files changed, 3 insertions(+) diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt index a8849c685c66..c1ee76347304 100644 --- a/bindings/clock/qcom,dispcc.txt +++ b/bindings/clock/qcom,dispcc.txt @@ -17,6 +17,7 @@ Required properties : "qcom,sm6150-dispcc" "qcom,sa6155-dispcc" "qcom,monaco-dispcc" + "qcom,blair-dispcc" - reg : shall contain base register location and length. - #clock-cells : from common clock binding, shall contain 1. diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt index a3097a70d4b0..b0919e3137e0 100644 --- a/bindings/clock/qcom,gcc.txt +++ b/bindings/clock/qcom,gcc.txt @@ -39,6 +39,7 @@ Required properties : "qcom,sa6155-gcc" "qcom,monaco-gcc" "qcom,direwolf-gcc" + "qcom,blair-gcc" - reg : shall contain base register location and length - vdd_cx-supply: The vdd_cx logic rail supply. diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt index bc6a3e2ce15a..03535db55849 100644 --- a/bindings/clock/qcom,gpucc.txt +++ b/bindings/clock/qcom,gpucc.txt @@ -13,6 +13,7 @@ Required properties : "qcom,sm6150-gpucc", "qcom,sa6155-gpucc". "qcom,monaco-gpucc" + "qcom,blair-gpucc" - reg: shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property.