From f5666717c7ceea6788214fa221ba5cd9de4d2390 Mon Sep 17 00:00:00 2001 From: Narendra Muppalla Date: Tue, 21 Jan 2020 18:49:48 -0800 Subject: [PATCH] disp: msm/sde: add CWB support for lahaina target This change updates the block offsets for concurrent writeback blocks and fixes the register dumping logic. Change-Id: I41b540773fea60e66cab5d476dff1a19b4f4b3db Signed-off-by: Narendra Muppalla --- msm/sde/sde_hw_catalog.c | 10 +++++++++- msm/sde/sde_hw_catalog.h | 4 ++++ msm/sde/sde_hw_wb.c | 23 +++++++++++++++-------- 3 files changed, 28 insertions(+), 9 deletions(-) diff --git a/msm/sde/sde_hw_catalog.c b/msm/sde/sde_hw_catalog.c index ed6126d3409c..5c06a445aeec 100644 --- a/msm/sde/sde_hw_catalog.c +++ b/msm/sde/sde_hw_catalog.c @@ -2117,7 +2117,7 @@ static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg) int rc, prop_count[WB_PROP_MAX], i, j; struct sde_prop_value *prop_value = NULL; bool prop_exists[WB_PROP_MAX]; - u32 off_count; + u32 off_count, major_version; struct sde_wb_cfg *wb; struct sde_wb_sub_blocks *sblk; @@ -2146,6 +2146,7 @@ static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg) if (rc) goto end; + major_version = SDE_HW_MAJOR(sde_cfg->hwversion); for (i = 0; i < off_count; i++) { wb = sde_cfg->wb + i; sblk = kzalloc(sizeof(*sblk), GFP_KERNEL); @@ -2208,6 +2209,13 @@ static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg) set_bit(SDE_WB_HAS_CWB, &wb->features); if (IS_SDE_CTL_REV_100(sde_cfg->ctl_rev)) set_bit(SDE_WB_CWB_CTRL, &wb->features); + if (major_version >= SDE_HW_MAJOR(SDE_HW_VER_700)) { + sde_cfg->cwb_blk_off = 0x6A200; + sde_cfg->cwb_blk_stride = 0x1000; + } else { + sde_cfg->cwb_blk_off = 0x83000; + sde_cfg->cwb_blk_stride = 0x100; + } } for (j = 0; j < sde_cfg->mdp_count; j++) { diff --git a/msm/sde/sde_hw_catalog.h b/msm/sde/sde_hw_catalog.h index cc7251279d72..d7e40af16709 100644 --- a/msm/sde/sde_hw_catalog.h +++ b/msm/sde/sde_hw_catalog.h @@ -1386,6 +1386,8 @@ struct sde_limit_cfg { * @has_cdp Client driven prefetch feature status * @has_wb_ubwc UBWC feature supported on WB * @has_cwb_support indicates if device supports primary capture through CWB + * @cwb_blk_off CWB offset address + * @cwb_blk_stride offset between each CWB blk * @ubwc_version UBWC feature version (0x0 for not supported) * @ubwc_bw_calc_version indicate how UBWC BW has to be calculated * @has_idle_pc indicate if idle power collapse feature is supported @@ -1451,6 +1453,8 @@ struct sde_mdss_cfg { bool has_dim_layer; bool has_wb_ubwc; bool has_cwb_support; + u32 cwb_blk_off; + u32 cwb_blk_stride; u32 ubwc_version; u32 ubwc_bw_calc_version; bool has_idle_pc; diff --git a/msm/sde/sde_hw_wb.c b/msm/sde/sde_hw_wb.c index df87f337ec51..277c1d7325f2 100644 --- a/msm/sde/sde_hw_wb.c +++ b/msm/sde/sde_hw_wb.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. */ #include "sde_hw_mdss.h" @@ -50,8 +50,6 @@ #define CWB_CTRL_SRC_SEL 0x0 #define CWB_CTRL_MODE 0x4 -#define CWB_CTRL_BLK_SIZE 0x100 -#define CWB_CTRL_BASE_OFFSET 0x83000 /* WB_QOS_CTRL */ #define WB_QOS_CTRL_DANGER_SAFE_EN BIT(0) @@ -79,15 +77,24 @@ static struct sde_wb_cfg *_wb_offset(enum sde_wb wb, static void _sde_hw_cwb_ctrl_init(struct sde_mdss_cfg *m, void __iomem *addr, struct sde_hw_blk_reg_map *b) { + int i; + u32 blk_off; + char name[64] = {0}; + if (b) { b->base_off = addr; - b->blk_off = CWB_CTRL_BASE_OFFSET; - b->length = CWB_CTRL_BLK_SIZE * m->pingpong_count; + b->blk_off = m->cwb_blk_off; + b->length = 0x20; b->hwversion = m->hwversion; b->log_mask = SDE_DBG_MASK_WB; + } - sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "cwb", b->blk_off, - b->blk_off + b->length, 0xff); + for (i = 0; i < m->pingpong_count; i++) { + snprintf(name, sizeof(name), "cwb%d", i); + blk_off = b->blk_off + (m->cwb_blk_stride * i); + + sde_dbg_reg_register_dump_range(SDE_DBG_NAME, name, + blk_off, blk_off + b->length, 0xff); } } @@ -291,7 +298,7 @@ static void sde_hw_wb_program_cwb_ctrl(struct sde_hw_wb *ctx, return; c = &ctx->cwb_hw; - blk_base = CWB_CTRL_BLK_SIZE * (cur_idx - CWB_0); + blk_base = ctx->catalog->cwb_blk_stride * (cur_idx - CWB_0); if (enable) { SDE_REG_WRITE(c, blk_base + CWB_CTRL_SRC_SEL, data_src - CWB_0);