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x86/events/amd/iommu.c: Modify functions to query max banks and counters
Currently, amd_iommu_pc_get_max_[banks|counters]() use end-point device ID to locate an IOMMU and check the reported max banks/counters. The logic assumes that the IOMMU_BASE_DEVID belongs to the first IOMMU, and uses it to acquire a reference to the first IOMMU, which does not work on certain systems. Instead, modify the function to take an IOMMU index, and use it to query the corresponding AMD IOMMU instance. Currently, hardcode the IOMMU index to 0 since the current AMD IOMMU perf implementation supports only a single IOMMU. A subsequent patch will add support for multiple IOMMUs, and will use a proper IOMMU index. Signed-off-by: Suravee Suthikulpanit <[email protected]> Signed-off-by: Borislav Petkov <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Cc: Alexander Shishkin <[email protected]> Cc: Arnaldo Carvalho de Melo <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: Jörg Rödel <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Stephane Eranian <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Vince Weaver <[email protected]> Cc: [email protected] Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
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4 changed files with 31 additions and 31 deletions
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@ -2718,6 +2718,18 @@ bool amd_iommu_v2_supported(void)
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}
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EXPORT_SYMBOL(amd_iommu_v2_supported);
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struct amd_iommu *get_amd_iommu(unsigned int idx)
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{
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unsigned int i = 0;
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struct amd_iommu *iommu;
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for_each_iommu(iommu)
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if (i++ == idx)
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return iommu;
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return NULL;
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}
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EXPORT_SYMBOL(get_amd_iommu);
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/****************************************************************************
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*
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* IOMMU EFR Performance Counter support functionality. This code allows
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@ -2725,17 +2737,14 @@ EXPORT_SYMBOL(amd_iommu_v2_supported);
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*
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****************************************************************************/
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u8 amd_iommu_pc_get_max_banks(u16 devid)
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u8 amd_iommu_pc_get_max_banks(unsigned int idx)
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{
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struct amd_iommu *iommu;
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u8 ret = 0;
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struct amd_iommu *iommu = get_amd_iommu(idx);
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/* locate the iommu governing the devid */
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iommu = amd_iommu_rlookup_table[devid];
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if (iommu)
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ret = iommu->max_banks;
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return iommu->max_banks;
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return ret;
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return 0;
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}
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EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
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@ -2745,17 +2754,14 @@ bool amd_iommu_pc_supported(void)
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}
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EXPORT_SYMBOL(amd_iommu_pc_supported);
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u8 amd_iommu_pc_get_max_counters(u16 devid)
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u8 amd_iommu_pc_get_max_counters(unsigned int idx)
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{
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struct amd_iommu *iommu;
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u8 ret = 0;
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struct amd_iommu *iommu = get_amd_iommu(idx);
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/* locate the iommu governing the devid */
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iommu = amd_iommu_rlookup_table[devid];
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if (iommu)
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ret = iommu->max_counters;
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return iommu->max_counters;
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return ret;
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return 0;
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}
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EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
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@ -59,8 +59,6 @@ extern struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev);
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/* IOMMU Performance Counter functions */
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extern bool amd_iommu_pc_supported(void);
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extern u8 amd_iommu_pc_get_max_banks(u16 devid);
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extern u8 amd_iommu_pc_get_max_counters(u16 devid);
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extern int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
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u64 *value, bool is_write);
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