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mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-28 10:41:38 -04:00
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Merge branches 'clk-qcom', 'clk-mtk', 'clk-armada', 'clk-ingenic' and 'clk-meson' into clk-next

Browse source 
- Support qcom SM8150 RPMh clks
 - Set floor ops for qcom sd clks
 - Support qcom QCS404 WCSS clks
 - Support for Mediatek MT6779 SoCs
 - Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807)

* clk-qcom:
  clk: qcom: rcg: Return failure for RCG update
  clk: qcom: fix QCS404 TuringCC regmap
  clk: qcom: clk-rpmh: Add support for SM8150
  dt-bindings: clock: Document SM8150 rpmh-clock compatible
  clk: qcom: clk-rpmh: Convert to parent data scheme
  dt-bindings: clock: Document the parent clocks
  clk: qcom: gcc: Use floor ops for SDCC clocks
  clk: qcom: gcc-qcs404: Use floor ops for sdcc clks
  clk: qcom: gcc-sdm845: Use floor ops for sdcc clks
  clk: qcom: define probe by index API as common API
  clk: qcom: Add WCSS gcc clock control for QCS404
  clk: qcom: msm8916: Don't build by default
  clk: qcom: gcc: Add global clock controller driver for SM8150
  dt-bindings: clock: Document gcc bindings for SM8150
  clk: qcom: clk-alpha-pll: Add support for Trion PLLs
  clk: qcom: clk-alpha-pll: Remove post_div_table checks
  clk: qcom: clk-alpha-pll: Remove unnecessary cast

* clk-mtk:
  clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider
  clk: mediatek: Register clock gate with device
  clk: mediatek: add pericfg clocks for MT8183
  dt-bindings: clock: mediatek: add pericfg for MT8183
  clk: mediatek: Add MT6779 clock support
  clk: mediatek: Add dt-bindings for MT6779 clocks
  dt-bindings: mediatek: bindings for MT6779 clk
  clk: reset: Modify reset-controller driver

* clk-armada:
  clk: mvebu: ap80x: add AP807 clock support
  clk: mvebu: ap806: Prepare the introduction of AP807 clock support
  clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver
  clk: mvebu: ap806: be more explicit on what SaR is
  clk: mvebu: ap80x-cpu: add AP807 CPU clock support
  clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock
  dt-bindings: ap806: Document AP807 clock compatible
  dt-bindings: ap80x: Document AP807 CPU clock compatible
  clk: mvebu: ap806: Fix clock name for the cluster
  clk: mvebu: add CPU clock driver for Armada 7K/8K
  clk: mvebu: add helper file for Armada AP and CP clocks
  dt-bindings: ap806: add the cluster clock node in the syscon file

* clk-ingenic:
  clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro
  clk: ingenic/jz4740: Fix "pll half" divider not read/written properly

* clk-meson: (23 commits)
  clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
  clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
  clk: meson: g12a: add support for SM1 GP1 PLL
  dt-bindings: clk: meson: add sm1 periph clock controller bindings
  clk: meson: axg-audio: add g12a reset support
  dt-bindings: clock: meson: add resets to the audio clock controller
  clk: meson: g12a: expose CPUB clock ID for G12B
  clk: meson: g12a: add notifiers to handle cpu clock change
  clk: meson: add g12a cpu dynamic divider driver
  clk: core: introduce clk_hw_set_parent()
  clk: meson: remove clk input helper
  clk: meson: remove ee input bypass clocks
  clk: meson: clk-regmap: migrate to new parent description method
  clk: meson: meson8b: migrate to the new parent description method
  clk: meson: axg: migrate to the new parent description method
  clk: meson: gxbb: migrate to the new parent description method
  clk: meson: g12a: migrate to the new parent description method
  clk: meson: remove ao input bypass clocks
  clk: meson: axg-aoclk: migrate to the new parent description method
  clk: meson: gxbb-aoclk: migrate to the new parent description method
  ...
This commit is contained in:
Stephen Boyd 2019-09-19 15:30:59 -07:00
commit f5c7305db3
92 changed files with 10804 additions and 1458 deletions
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6
include/dt-bindings/clock/g12a-clkc.h
View file

@ -137,5 +137,11 @@
#define CLKID_VDEC_HEVC 207
#define CLKID_VDEC_HEVCF 210
#define CLKID_TS 212
#define CLKID_CPUB_CLK 224
#define CLKID_GP1_PLL 243
#define CLKID_DSU_CLK 252
#define CLKID_CPU1_CLK 253
#define CLKID_CPU2_CLK 254
#define CLKID_CPU3_CLK 255
#endif /* __G12A_CLKC_H */

436
include/dt-bindings/clock/mt6779-clk.h Normal file
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@ -0,0 +1,436 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Wendell Lin <wendell.lin@mediatek.com>
*/
#ifndef _DT_BINDINGS_CLK_MT6779_H
#define _DT_BINDINGS_CLK_MT6779_H
/* TOPCKGEN */
#define CLK_TOP_AXI 1
#define CLK_TOP_MM 2
#define CLK_TOP_CAM 3
#define CLK_TOP_MFG 4
#define CLK_TOP_CAMTG 5
#define CLK_TOP_UART 6
#define CLK_TOP_SPI 7
#define CLK_TOP_MSDC50_0_HCLK 8
#define CLK_TOP_MSDC50_0 9
#define CLK_TOP_MSDC30_1 10
#define CLK_TOP_MSDC30_2 11
#define CLK_TOP_AUD 12
#define CLK_TOP_AUD_INTBUS 13
#define CLK_TOP_FPWRAP_ULPOSC 14
#define CLK_TOP_SCP 15
#define CLK_TOP_ATB 16
#define CLK_TOP_SSPM 17
#define CLK_TOP_DPI0 18
#define CLK_TOP_SCAM 19
#define CLK_TOP_AUD_1 20
#define CLK_TOP_AUD_2 21
#define CLK_TOP_DISP_PWM 22
#define CLK_TOP_SSUSB_TOP_XHCI 23
#define CLK_TOP_USB_TOP 24
#define CLK_TOP_SPM 25
#define CLK_TOP_I2C 26
#define CLK_TOP_F52M_MFG 27
#define CLK_TOP_SENINF 28
#define CLK_TOP_DXCC 29
#define CLK_TOP_CAMTG2 30
#define CLK_TOP_AUD_ENG1 31
#define CLK_TOP_AUD_ENG2 32
#define CLK_TOP_FAES_UFSFDE 33
#define CLK_TOP_FUFS 34
#define CLK_TOP_IMG 35
#define CLK_TOP_DSP 36
#define CLK_TOP_DSP1 37
#define CLK_TOP_DSP2 38
#define CLK_TOP_IPU_IF 39
#define CLK_TOP_CAMTG3 40
#define CLK_TOP_CAMTG4 41
#define CLK_TOP_PMICSPI 42
#define CLK_TOP_MAINPLL_CK 43
#define CLK_TOP_MAINPLL_D2 44
#define CLK_TOP_MAINPLL_D3 45
#define CLK_TOP_MAINPLL_D5 46
#define CLK_TOP_MAINPLL_D7 47
#define CLK_TOP_MAINPLL_D2_D2 48
#define CLK_TOP_MAINPLL_D2_D4 49
#define CLK_TOP_MAINPLL_D2_D8 50
#define CLK_TOP_MAINPLL_D2_D16 51
#define CLK_TOP_MAINPLL_D3_D2 52
#define CLK_TOP_MAINPLL_D3_D4 53
#define CLK_TOP_MAINPLL_D3_D8 54
#define CLK_TOP_MAINPLL_D5_D2 55
#define CLK_TOP_MAINPLL_D5_D4 56
#define CLK_TOP_MAINPLL_D7_D2 57
#define CLK_TOP_MAINPLL_D7_D4 58
#define CLK_TOP_UNIVPLL_CK 59
#define CLK_TOP_UNIVPLL_D2 60
#define CLK_TOP_UNIVPLL_D3 61
#define CLK_TOP_UNIVPLL_D5 62
#define CLK_TOP_UNIVPLL_D7 63
#define CLK_TOP_UNIVPLL_D2_D2 64
#define CLK_TOP_UNIVPLL_D2_D4 65
#define CLK_TOP_UNIVPLL_D2_D8 66
#define CLK_TOP_UNIVPLL_D3_D2 67
#define CLK_TOP_UNIVPLL_D3_D4 68
#define CLK_TOP_UNIVPLL_D3_D8 69
#define CLK_TOP_UNIVPLL_D5_D2 70
#define CLK_TOP_UNIVPLL_D5_D4 71
#define CLK_TOP_UNIVPLL_D5_D8 72
#define CLK_TOP_APLL1_CK 73
#define CLK_TOP_APLL1_D2 74
#define CLK_TOP_APLL1_D4 75
#define CLK_TOP_APLL1_D8 76
#define CLK_TOP_APLL2_CK 77
#define CLK_TOP_APLL2_D2 78
#define CLK_TOP_APLL2_D4 79
#define CLK_TOP_APLL2_D8 80
#define CLK_TOP_TVDPLL_CK 81
#define CLK_TOP_TVDPLL_D2 82
#define CLK_TOP_TVDPLL_D4 83
#define CLK_TOP_TVDPLL_D8 84
#define CLK_TOP_TVDPLL_D16 85
#define CLK_TOP_MSDCPLL_CK 86
#define CLK_TOP_MSDCPLL_D2 87
#define CLK_TOP_MSDCPLL_D4 88
#define CLK_TOP_MSDCPLL_D8 89
#define CLK_TOP_MSDCPLL_D16 90
#define CLK_TOP_AD_OSC_CK 91
#define CLK_TOP_OSC_D2 92
#define CLK_TOP_OSC_D4 93
#define CLK_TOP_OSC_D8 94
#define CLK_TOP_OSC_D16 95
#define CLK_TOP_F26M_CK_D2 96
#define CLK_TOP_MFGPLL_CK 97
#define CLK_TOP_UNIVP_192M_CK 98
#define CLK_TOP_UNIVP_192M_D2 99
#define CLK_TOP_UNIVP_192M_D4 100
#define CLK_TOP_UNIVP_192M_D8 101
#define CLK_TOP_UNIVP_192M_D16 102
#define CLK_TOP_UNIVP_192M_D32 103
#define CLK_TOP_MMPLL_CK 104
#define CLK_TOP_MMPLL_D4 105
#define CLK_TOP_MMPLL_D4_D2 106
#define CLK_TOP_MMPLL_D4_D4 107
#define CLK_TOP_MMPLL_D5 108
#define CLK_TOP_MMPLL_D5_D2 109
#define CLK_TOP_MMPLL_D5_D4 110
#define CLK_TOP_MMPLL_D6 111
#define CLK_TOP_MMPLL_D7 112
#define CLK_TOP_CLK26M 113
#define CLK_TOP_CLK13M 114
#define CLK_TOP_ADSP 115
#define CLK_TOP_DPMAIF 116
#define CLK_TOP_VENC 117
#define CLK_TOP_VDEC 118
#define CLK_TOP_CAMTM 119
#define CLK_TOP_PWM 120
#define CLK_TOP_ADSPPLL_CK 121
#define CLK_TOP_I2S0_M_SEL 122
#define CLK_TOP_I2S1_M_SEL 123
#define CLK_TOP_I2S2_M_SEL 124
#define CLK_TOP_I2S3_M_SEL 125
#define CLK_TOP_I2S4_M_SEL 126
#define CLK_TOP_I2S5_M_SEL 127
#define CLK_TOP_APLL12_DIV0 128
#define CLK_TOP_APLL12_DIV1 129
#define CLK_TOP_APLL12_DIV2 130
#define CLK_TOP_APLL12_DIV3 131
#define CLK_TOP_APLL12_DIV4 132
#define CLK_TOP_APLL12_DIVB 133
#define CLK_TOP_APLL12_DIV5 134
#define CLK_TOP_IPE 135
#define CLK_TOP_DPE 136
#define CLK_TOP_CCU 137
#define CLK_TOP_DSP3 138
#define CLK_TOP_SENINF1 139
#define CLK_TOP_SENINF2 140
#define CLK_TOP_AUD_H 141
#define CLK_TOP_CAMTG5 142
#define CLK_TOP_TVDPLL_MAINPLL_D2_CK 143
#define CLK_TOP_AD_OSC2_CK 144
#define CLK_TOP_OSC2_D2 145
#define CLK_TOP_OSC2_D3 146
#define CLK_TOP_FMEM_466M_CK 147
#define CLK_TOP_ADSPPLL_D4 148
#define CLK_TOP_ADSPPLL_D5 149
#define CLK_TOP_ADSPPLL_D6 150
#define CLK_TOP_OSC_D10 151
#define CLK_TOP_UNIVPLL_D3_D16 152
#define CLK_TOP_NR_CLK 153
/* APMIXED */
#define CLK_APMIXED_ARMPLL_LL 1
#define CLK_APMIXED_ARMPLL_BL 2
#define CLK_APMIXED_ARMPLL_BB 3
#define CLK_APMIXED_CCIPLL 4
#define CLK_APMIXED_MAINPLL 5
#define CLK_APMIXED_UNIV2PLL 6
#define CLK_APMIXED_MSDCPLL 7
#define CLK_APMIXED_ADSPPLL 8
#define CLK_APMIXED_MMPLL 9
#define CLK_APMIXED_MFGPLL 10
#define CLK_APMIXED_TVDPLL 11
#define CLK_APMIXED_APLL1 12
#define CLK_APMIXED_APLL2 13
#define CLK_APMIXED_SSUSB26M 14
#define CLK_APMIXED_APPLL26M 15
#define CLK_APMIXED_MIPIC0_26M 16
#define CLK_APMIXED_MDPLLGP26M 17
#define CLK_APMIXED_MM_F26M 18
#define CLK_APMIXED_UFS26M 19
#define CLK_APMIXED_MIPIC1_26M 20
#define CLK_APMIXED_MEMPLL26M 21
#define CLK_APMIXED_CLKSQ_LVPLL_26M 22
#define CLK_APMIXED_MIPID0_26M 23
#define CLK_APMIXED_MIPID1_26M 24
#define CLK_APMIXED_NR_CLK 25
/* CAMSYS */
#define CLK_CAM_LARB10 1
#define CLK_CAM_DFP_VAD 2
#define CLK_CAM_LARB11 3
#define CLK_CAM_LARB9 4
#define CLK_CAM_CAM 5
#define CLK_CAM_CAMTG 6
#define CLK_CAM_SENINF 7
#define CLK_CAM_CAMSV0 8
#define CLK_CAM_CAMSV1 9
#define CLK_CAM_CAMSV2 10
#define CLK_CAM_CAMSV3 11
#define CLK_CAM_CCU 12
#define CLK_CAM_FAKE_ENG 13
#define CLK_CAM_NR_CLK 14
/* INFRA */
#define CLK_INFRA_PMIC_TMR 1
#define CLK_INFRA_PMIC_AP 2
#define CLK_INFRA_PMIC_MD 3
#define CLK_INFRA_PMIC_CONN 4
#define CLK_INFRA_SCPSYS 5
#define CLK_INFRA_SEJ 6
#define CLK_INFRA_APXGPT 7
#define CLK_INFRA_ICUSB 8
#define CLK_INFRA_GCE 9
#define CLK_INFRA_THERM 10
#define CLK_INFRA_I2C0 11
#define CLK_INFRA_I2C1 12
#define CLK_INFRA_I2C2 13
#define CLK_INFRA_I2C3 14
#define CLK_INFRA_PWM_HCLK 15
#define CLK_INFRA_PWM1 16
#define CLK_INFRA_PWM2 17
#define CLK_INFRA_PWM3 18
#define CLK_INFRA_PWM4 19
#define CLK_INFRA_PWM 20
#define CLK_INFRA_UART0 21
#define CLK_INFRA_UART1 22
#define CLK_INFRA_UART2 23
#define CLK_INFRA_UART3 24
#define CLK_INFRA_GCE_26M 25
#define CLK_INFRA_CQ_DMA_FPC 26
#define CLK_INFRA_BTIF 27
#define CLK_INFRA_SPI0 28
#define CLK_INFRA_MSDC0 29
#define CLK_INFRA_MSDC1 30
#define CLK_INFRA_MSDC2 31
#define CLK_INFRA_MSDC0_SCK 32
#define CLK_INFRA_DVFSRC 33
#define CLK_INFRA_GCPU 34
#define CLK_INFRA_TRNG 35
#define CLK_INFRA_AUXADC 36
#define CLK_INFRA_CPUM 37
#define CLK_INFRA_CCIF1_AP 38
#define CLK_INFRA_CCIF1_MD 39
#define CLK_INFRA_AUXADC_MD 40
#define CLK_INFRA_MSDC1_SCK 41
#define CLK_INFRA_MSDC2_SCK 42
#define CLK_INFRA_AP_DMA 43
#define CLK_INFRA_XIU 44
#define CLK_INFRA_DEVICE_APC 45
#define CLK_INFRA_CCIF_AP 46
#define CLK_INFRA_DEBUGSYS 47
#define CLK_INFRA_AUD 48
#define CLK_INFRA_CCIF_MD 49
#define CLK_INFRA_DXCC_SEC_CORE 50
#define CLK_INFRA_DXCC_AO 51
#define CLK_INFRA_DRAMC_F26M 52
#define CLK_INFRA_IRTX 53
#define CLK_INFRA_DISP_PWM 54
#define CLK_INFRA_DPMAIF_CK 55
#define CLK_INFRA_AUD_26M_BCLK 56
#define CLK_INFRA_SPI1 57
#define CLK_INFRA_I2C4 58
#define CLK_INFRA_MODEM_TEMP_SHARE 59
#define CLK_INFRA_SPI2 60
#define CLK_INFRA_SPI3 61
#define CLK_INFRA_UNIPRO_SCK 62
#define CLK_INFRA_UNIPRO_TICK 63
#define CLK_INFRA_UFS_MP_SAP_BCLK 64
#define CLK_INFRA_MD32_BCLK 65
#define CLK_INFRA_SSPM 66
#define CLK_INFRA_UNIPRO_MBIST 67
#define CLK_INFRA_SSPM_BUS_HCLK 68
#define CLK_INFRA_I2C5 69
#define CLK_INFRA_I2C5_ARBITER 70
#define CLK_INFRA_I2C5_IMM 71
#define CLK_INFRA_I2C1_ARBITER 72
#define CLK_INFRA_I2C1_IMM 73
#define CLK_INFRA_I2C2_ARBITER 74
#define CLK_INFRA_I2C2_IMM 75
#define CLK_INFRA_SPI4 76
#define CLK_INFRA_SPI5 77
#define CLK_INFRA_CQ_DMA 78
#define CLK_INFRA_UFS 79
#define CLK_INFRA_AES_UFSFDE 80
#define CLK_INFRA_UFS_TICK 81
#define CLK_INFRA_MSDC0_SELF 82
#define CLK_INFRA_MSDC1_SELF 83
#define CLK_INFRA_MSDC2_SELF 84
#define CLK_INFRA_SSPM_26M_SELF 85
#define CLK_INFRA_SSPM_32K_SELF 86
#define CLK_INFRA_UFS_AXI 87
#define CLK_INFRA_I2C6 88
#define CLK_INFRA_AP_MSDC0 89
#define CLK_INFRA_MD_MSDC0 90
#define CLK_INFRA_USB 91
#define CLK_INFRA_DEVMPU_BCLK 92
#define CLK_INFRA_CCIF2_AP 93
#define CLK_INFRA_CCIF2_MD 94
#define CLK_INFRA_CCIF3_AP 95
#define CLK_INFRA_CCIF3_MD 96
#define CLK_INFRA_SEJ_F13M 97
#define CLK_INFRA_AES_BCLK 98
#define CLK_INFRA_I2C7 99
#define CLK_INFRA_I2C8 100
#define CLK_INFRA_FBIST2FPC 101
#define CLK_INFRA_CCIF4_AP 102
#define CLK_INFRA_CCIF4_MD 103
#define CLK_INFRA_FADSP 104
#define CLK_INFRA_SSUSB_XHCI 105
#define CLK_INFRA_SPI6 106
#define CLK_INFRA_SPI7 107
#define CLK_INFRA_NR_CLK 108
/* MFGCFG */
#define CLK_MFGCFG_BG3D 1
#define CLK_MFGCFG_NR_CLK 2
/* IMG */
#define CLK_IMG_WPE_A 1
#define CLK_IMG_MFB 2
#define CLK_IMG_DIP 3
#define CLK_IMG_LARB6 4
#define CLK_IMG_LARB5 5
#define CLK_IMG_NR_CLK 6
/* IPE */
#define CLK_IPE_LARB7 1
#define CLK_IPE_LARB8 2
#define CLK_IPE_SMI_SUBCOM 3
#define CLK_IPE_FD 4
#define CLK_IPE_FE 5
#define CLK_IPE_RSC 6
#define CLK_IPE_DPE 7
#define CLK_IPE_NR_CLK 8
/* MM_CONFIG */
#define CLK_MM_SMI_COMMON 1
#define CLK_MM_SMI_LARB0 2
#define CLK_MM_SMI_LARB1 3
#define CLK_MM_GALS_COMM0 4
#define CLK_MM_GALS_COMM1 5
#define CLK_MM_GALS_CCU2MM 6
#define CLK_MM_GALS_IPU12MM 7
#define CLK_MM_GALS_IMG2MM 8
#define CLK_MM_GALS_CAM2MM 9
#define CLK_MM_GALS_IPU2MM 10
#define CLK_MM_MDP_DL_TXCK 11
#define CLK_MM_IPU_DL_TXCK 12
#define CLK_MM_MDP_RDMA0 13
#define CLK_MM_MDP_RDMA1 14
#define CLK_MM_MDP_RSZ0 15
#define CLK_MM_MDP_RSZ1 16
#define CLK_MM_MDP_TDSHP 17
#define CLK_MM_MDP_WROT0 18
#define CLK_MM_FAKE_ENG 19
#define CLK_MM_DISP_OVL0 20
#define CLK_MM_DISP_OVL0_2L 21
#define CLK_MM_DISP_OVL1_2L 22
#define CLK_MM_DISP_RDMA0 23
#define CLK_MM_DISP_RDMA1 24
#define CLK_MM_DISP_WDMA0 25
#define CLK_MM_DISP_COLOR0 26
#define CLK_MM_DISP_CCORR0 27
#define CLK_MM_DISP_AAL0 28
#define CLK_MM_DISP_GAMMA0 29
#define CLK_MM_DISP_DITHER0 30
#define CLK_MM_DISP_SPLIT 31
#define CLK_MM_DSI0_MM_CK 32
#define CLK_MM_DSI0_IF_CK 33
#define CLK_MM_DPI_MM_CK 34
#define CLK_MM_DPI_IF_CK 35
#define CLK_MM_FAKE_ENG2 36
#define CLK_MM_MDP_DL_RX_CK 37
#define CLK_MM_IPU_DL_RX_CK 38
#define CLK_MM_26M 39
#define CLK_MM_MM_R2Y 40
#define CLK_MM_DISP_RSZ 41
#define CLK_MM_MDP_WDMA0 42
#define CLK_MM_MDP_AAL 43
#define CLK_MM_MDP_HDR 44
#define CLK_MM_DBI_MM_CK 45
#define CLK_MM_DBI_IF_CK 46
#define CLK_MM_MDP_WROT1 47
#define CLK_MM_DISP_POSTMASK0 48
#define CLK_MM_DISP_HRT_BW 49
#define CLK_MM_DISP_OVL_FBDC 50
#define CLK_MM_NR_CLK 51
/* VDEC_GCON */
#define CLK_VDEC_VDEC 1
#define CLK_VDEC_LARB1 2
#define CLK_VDEC_GCON_NR_CLK 3
/* VENC_GCON */
#define CLK_VENC_GCON_LARB 1
#define CLK_VENC_GCON_VENC 2
#define CLK_VENC_GCON_JPGENC 3
#define CLK_VENC_GCON_GALS 4
#define CLK_VENC_GCON_NR_CLK 5
/* AUD */
#define CLK_AUD_AFE 1
#define CLK_AUD_22M 2
#define CLK_AUD_24M 3
#define CLK_AUD_APLL2_TUNER 4
#define CLK_AUD_APLL_TUNER 5
#define CLK_AUD_TDM 6
#define CLK_AUD_ADC 7
#define CLK_AUD_DAC 8
#define CLK_AUD_DAC_PREDIS 9
#define CLK_AUD_TML 10
#define CLK_AUD_NLE 11
#define CLK_AUD_I2S1_BCLK_SW 12
#define CLK_AUD_I2S2_BCLK_SW 13
#define CLK_AUD_I2S3_BCLK_SW 14
#define CLK_AUD_I2S4_BCLK_SW 15
#define CLK_AUD_I2S5_BCLK_SW 16
#define CLK_AUD_CONN_I2S_ASRC 17
#define CLK_AUD_GENERAL1_ASRC 18
#define CLK_AUD_GENERAL2_ASRC 19
#define CLK_AUD_DAC_HIRES 20
#define CLK_AUD_PDN_ADDA6_ADC 21
#define CLK_AUD_ADC_HIRES 22
#define CLK_AUD_ADC_HIRES_TML 23
#define CLK_AUD_ADDA6_ADC_HIRES 24
#define CLK_AUD_3RD_DAC 25
#define CLK_AUD_3RD_DAC_PREDIS 26
#define CLK_AUD_3RD_DAC_TML 27
#define CLK_AUD_3RD_DAC_HIRES 28
#define CLK_AUD_NR_CLK 29
#endif /* _DT_BINDINGS_CLK_MT6779_H */

4
include/dt-bindings/clock/mt8183-clk.h
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@ -284,6 +284,10 @@
#define CLK_INFRA_FBIST2FPC 100
#define CLK_INFRA_NR_CLK 101
/* PERICFG */
#define CLK_PERI_AXI 0
#define CLK_PERI_NR_CLK 1
/* MFGCFG */
#define CLK_MFG_BG3D 0
#define CLK_MFG_NR_CLK 1

3
include/dt-bindings/clock/qcom,gcc-qcs404.h
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@ -146,6 +146,8 @@
#define GCC_MDP_TBU_CLK 138
#define GCC_QDSS_DAP_CLK 139
#define GCC_DCC_XO_CLK 140
#define GCC_WCSS_Q6_AHB_CLK 141
#define GCC_WCSS_Q6_AXIM_CLK 142
#define GCC_CDSP_CFG_AHB_CLK 143
#define GCC_BIMC_CDSP_CLK 144
#define GCC_CDSP_TBU_CLK 145
@ -173,5 +175,6 @@
#define GCC_PCIE_0_CORE_STICKY_ARES 19
#define GCC_PCIE_0_SLEEP_ARES 20
#define GCC_PCIE_0_PIPE_ARES 21
#define GCC_WDSP_RESTART 22
#endif

243
include/dt-bindings/clock/qcom,gcc-sm8150.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H
#define _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H
/* GCC clocks */
#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 2
#define GCC_AGGRE_UFS_PHY_AXI_CLK 3
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 4
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5
#define GCC_AGGRE_USB3_SEC_AXI_CLK 6
#define GCC_BOOT_ROM_AHB_CLK 7
#define GCC_CAMERA_AHB_CLK 8
#define GCC_CAMERA_HF_AXI_CLK 9
#define GCC_CAMERA_SF_AXI_CLK 10
#define GCC_CAMERA_XO_CLK 11
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12
#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13
#define GCC_CPUSS_AHB_CLK 14
#define GCC_CPUSS_AHB_CLK_SRC 15
#define GCC_CPUSS_DVM_BUS_CLK 16
#define GCC_CPUSS_GNOC_CLK 17
#define GCC_CPUSS_RBCPR_CLK 18
#define GCC_DDRSS_GPU_AXI_CLK 19
#define GCC_DISP_AHB_CLK 20
#define GCC_DISP_HF_AXI_CLK 21
#define GCC_DISP_SF_AXI_CLK 22
#define GCC_DISP_XO_CLK 23
#define GCC_EMAC_AXI_CLK 24
#define GCC_EMAC_PTP_CLK 25
#define GCC_EMAC_PTP_CLK_SRC 26
#define GCC_EMAC_RGMII_CLK 27
#define GCC_EMAC_RGMII_CLK_SRC 28
#define GCC_EMAC_SLV_AHB_CLK 29
#define GCC_GP1_CLK 30
#define GCC_GP1_CLK_SRC 31
#define GCC_GP2_CLK 32
#define GCC_GP2_CLK_SRC 33
#define GCC_GP3_CLK 34
#define GCC_GP3_CLK_SRC 35
#define GCC_GPU_CFG_AHB_CLK 36
#define GCC_GPU_GPLL0_CLK_SRC 37
#define GCC_GPU_GPLL0_DIV_CLK_SRC 38
#define GCC_GPU_IREF_CLK 39
#define GCC_GPU_MEMNOC_GFX_CLK 40
#define GCC_GPU_SNOC_DVM_GFX_CLK 41
#define GCC_NPU_AT_CLK 42
#define GCC_NPU_AXI_CLK 43
#define GCC_NPU_CFG_AHB_CLK 44
#define GCC_NPU_GPLL0_CLK_SRC 45
#define GCC_NPU_GPLL0_DIV_CLK_SRC 46
#define GCC_NPU_TRIG_CLK 47
#define GCC_PCIE0_PHY_REFGEN_CLK 48
#define GCC_PCIE1_PHY_REFGEN_CLK 49
#define GCC_PCIE_0_AUX_CLK 50
#define GCC_PCIE_0_AUX_CLK_SRC 51
#define GCC_PCIE_0_CFG_AHB_CLK 52
#define GCC_PCIE_0_CLKREF_CLK 53
#define GCC_PCIE_0_MSTR_AXI_CLK 54
#define GCC_PCIE_0_PIPE_CLK 55
#define GCC_PCIE_0_SLV_AXI_CLK 56
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57
#define GCC_PCIE_1_AUX_CLK 58
#define GCC_PCIE_1_AUX_CLK_SRC 59
#define GCC_PCIE_1_CFG_AHB_CLK 60
#define GCC_PCIE_1_CLKREF_CLK 61
#define GCC_PCIE_1_MSTR_AXI_CLK 62
#define GCC_PCIE_1_PIPE_CLK 63
#define GCC_PCIE_1_SLV_AXI_CLK 64
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 65
#define GCC_PCIE_PHY_AUX_CLK 66
#define GCC_PCIE_PHY_REFGEN_CLK_SRC 67
#define GCC_PDM2_CLK 68
#define GCC_PDM2_CLK_SRC 69
#define GCC_PDM_AHB_CLK 70
#define GCC_PDM_XO4_CLK 71
#define GCC_PRNG_AHB_CLK 72
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 73
#define GCC_QMIP_CAMERA_RT_AHB_CLK 74
#define GCC_QMIP_DISP_AHB_CLK 75
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 76
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 77
#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 78
#define GCC_QSPI_CORE_CLK 79
#define GCC_QSPI_CORE_CLK_SRC 80
#define GCC_QUPV3_WRAP0_S0_CLK 81
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 82
#define GCC_QUPV3_WRAP0_S1_CLK 83
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 84
#define GCC_QUPV3_WRAP0_S2_CLK 85
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 86
#define GCC_QUPV3_WRAP0_S3_CLK 87
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 88
#define GCC_QUPV3_WRAP0_S4_CLK 89
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 90
#define GCC_QUPV3_WRAP0_S5_CLK 91
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 92
#define GCC_QUPV3_WRAP0_S6_CLK 93
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 94
#define GCC_QUPV3_WRAP0_S7_CLK 95
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 96
#define GCC_QUPV3_WRAP1_S0_CLK 97
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 98
#define GCC_QUPV3_WRAP1_S1_CLK 99
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 100
#define GCC_QUPV3_WRAP1_S2_CLK 101
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 102
#define GCC_QUPV3_WRAP1_S3_CLK 103
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 104
#define GCC_QUPV3_WRAP1_S4_CLK 105
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 106
#define GCC_QUPV3_WRAP1_S5_CLK 107
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 108
#define GCC_QUPV3_WRAP2_S0_CLK 109
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 110
#define GCC_QUPV3_WRAP2_S1_CLK 111
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 112
#define GCC_QUPV3_WRAP2_S2_CLK 113
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 114
#define GCC_QUPV3_WRAP2_S3_CLK 115
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 116
#define GCC_QUPV3_WRAP2_S4_CLK 117
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 118
#define GCC_QUPV3_WRAP2_S5_CLK 119
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 120
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 121
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 122
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 123
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 124
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 125
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 126
#define GCC_SDCC2_AHB_CLK 127
#define GCC_SDCC2_APPS_CLK 128
#define GCC_SDCC2_APPS_CLK_SRC 129
#define GCC_SDCC4_AHB_CLK 130
#define GCC_SDCC4_APPS_CLK 131
#define GCC_SDCC4_APPS_CLK_SRC 132
#define GCC_SYS_NOC_CPUSS_AHB_CLK 133
#define GCC_TSIF_AHB_CLK 134
#define GCC_TSIF_INACTIVITY_TIMERS_CLK 135
#define GCC_TSIF_REF_CLK 136
#define GCC_TSIF_REF_CLK_SRC 137
#define GCC_UFS_CARD_AHB_CLK 138
#define GCC_UFS_CARD_AXI_CLK 139
#define GCC_UFS_CARD_AXI_CLK_SRC 140
#define GCC_UFS_CARD_AXI_HW_CTL_CLK 141
#define GCC_UFS_CARD_CLKREF_CLK 142
#define GCC_UFS_CARD_ICE_CORE_CLK 143
#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 144
#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 145
#define GCC_UFS_CARD_PHY_AUX_CLK 146
#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 147
#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 148
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 149
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 150
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 151
#define GCC_UFS_CARD_UNIPRO_CORE_CLK 152
#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 153
#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 154
#define GCC_UFS_MEM_CLKREF_CLK 155
#define GCC_UFS_PHY_AHB_CLK 156
#define GCC_UFS_PHY_AXI_CLK 157
#define GCC_UFS_PHY_AXI_CLK_SRC 158
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 159
#define GCC_UFS_PHY_ICE_CORE_CLK 160
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 161
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 162
#define GCC_UFS_PHY_PHY_AUX_CLK 163
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 164
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 165
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 166
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 167
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 169
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 170
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 171
#define GCC_USB30_PRIM_MASTER_CLK 172
#define GCC_USB30_PRIM_MASTER_CLK_SRC 173
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 174
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 175
#define GCC_USB30_PRIM_SLEEP_CLK 176
#define GCC_USB30_SEC_MASTER_CLK 177
#define GCC_USB30_SEC_MASTER_CLK_SRC 178
#define GCC_USB30_SEC_MOCK_UTMI_CLK 179
#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 180
#define GCC_USB30_SEC_SLEEP_CLK 181
#define GCC_USB3_PRIM_CLKREF_CLK 182
#define GCC_USB3_PRIM_PHY_AUX_CLK 183
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 184
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 185
#define GCC_USB3_PRIM_PHY_PIPE_CLK 186
#define GCC_USB3_SEC_CLKREF_CLK 187
#define GCC_USB3_SEC_PHY_AUX_CLK 188
#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 189
#define GCC_USB3_SEC_PHY_COM_AUX_CLK 190
#define GCC_USB3_SEC_PHY_PIPE_CLK 191
#define GCC_VIDEO_AHB_CLK 192
#define GCC_VIDEO_AXI0_CLK 193
#define GCC_VIDEO_AXI1_CLK 194
#define GCC_VIDEO_AXIC_CLK 195
#define GCC_VIDEO_XO_CLK 196
#define GPLL0 197
#define GPLL0_OUT_EVEN 198
#define GPLL7 199
#define GPLL9 200
/* Reset clocks */
#define GCC_EMAC_BCR 0
#define GCC_GPU_BCR 1
#define GCC_MMSS_BCR 2
#define GCC_NPU_BCR 3
#define GCC_PCIE_0_BCR 4
#define GCC_PCIE_0_PHY_BCR 5
#define GCC_PCIE_1_BCR 6
#define GCC_PCIE_1_PHY_BCR 7
#define GCC_PCIE_PHY_BCR 8
#define GCC_PDM_BCR 9
#define GCC_PRNG_BCR 10
#define GCC_QSPI_BCR 11
#define GCC_QUPV3_WRAPPER_0_BCR 12
#define GCC_QUPV3_WRAPPER_1_BCR 13
#define GCC_QUPV3_WRAPPER_2_BCR 14
#define GCC_QUSB2PHY_PRIM_BCR 15
#define GCC_QUSB2PHY_SEC_BCR 16
#define GCC_USB3_PHY_PRIM_BCR 17
#define GCC_USB3_DP_PHY_PRIM_BCR 18
#define GCC_USB3_PHY_SEC_BCR 19
#define GCC_USB3PHY_PHY_SEC_BCR 20
#define GCC_SDCC2_BCR 21
#define GCC_SDCC4_BCR 22
#define GCC_TSIF_BCR 23
#define GCC_UFS_CARD_BCR 24
#define GCC_UFS_PHY_BCR 25
#define GCC_USB30_PRIM_BCR 26
#define GCC_USB30_SEC_BCR 27
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28
#endif

81
include/dt-bindings/reset-controller/mt8183-resets.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Yong Liang <yong.liang@mediatek.com>
*/
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8183
#define _DT_BINDINGS_RESET_CONTROLLER_MT8183
/* INFRACFG AO resets */
#define MT8183_INFRACFG_AO_THERM_SW_RST 0
#define MT8183_INFRACFG_AO_USB_TOP_SW_RST 1
#define MT8183_INFRACFG_AO_MM_IOMMU_SW_RST 3
#define MT8183_INFRACFG_AO_MSDC3_SW_RST 4
#define MT8183_INFRACFG_AO_MSDC2_SW_RST 5
#define MT8183_INFRACFG_AO_MSDC1_SW_RST 6
#define MT8183_INFRACFG_AO_MSDC0_SW_RST 7
#define MT8183_INFRACFG_AO_APDMA_SW_RST 9
#define MT8183_INFRACFG_AO_MIMP_D_SW_RST 10
#define MT8183_INFRACFG_AO_BTIF_SW_RST 12
#define MT8183_INFRACFG_AO_DISP_PWM_SW_RST 14
#define MT8183_INFRACFG_AO_AUXADC_SW_RST 15
#define MT8183_INFRACFG_AO_IRTX_SW_RST 32
#define MT8183_INFRACFG_AO_SPI0_SW_RST 33
#define MT8183_INFRACFG_AO_I2C0_SW_RST 34
#define MT8183_INFRACFG_AO_I2C1_SW_RST 35
#define MT8183_INFRACFG_AO_I2C2_SW_RST 36
#define MT8183_INFRACFG_AO_I2C3_SW_RST 37
#define MT8183_INFRACFG_AO_UART0_SW_RST 38
#define MT8183_INFRACFG_AO_UART1_SW_RST 39
#define MT8183_INFRACFG_AO_UART2_SW_RST 40
#define MT8183_INFRACFG_AO_PWM_SW_RST 41
#define MT8183_INFRACFG_AO_SPI1_SW_RST 42
#define MT8183_INFRACFG_AO_I2C4_SW_RST 43
#define MT8183_INFRACFG_AO_DVFSP_SW_RST 44
#define MT8183_INFRACFG_AO_SPI2_SW_RST 45
#define MT8183_INFRACFG_AO_SPI3_SW_RST 46
#define MT8183_INFRACFG_AO_UFSHCI_SW_RST 47
#define MT8183_INFRACFG_AO_PMIC_WRAP_SW_RST 64
#define MT8183_INFRACFG_AO_SPM_SW_RST 65
#define MT8183_INFRACFG_AO_USBSIF_SW_RST 66
#define MT8183_INFRACFG_AO_KP_SW_RST 68
#define MT8183_INFRACFG_AO_APXGPT_SW_RST 69
#define MT8183_INFRACFG_AO_CLDMA_AO_SW_RST 70
#define MT8183_INFRACFG_AO_UNIPRO_UFS_SW_RST 71
#define MT8183_INFRACFG_AO_DX_CC_SW_RST 72
#define MT8183_INFRACFG_AO_UFSPHY_SW_RST 73
#define MT8183_INFRACFG_AO_DX_CC_SEC_SW_RST 96
#define MT8183_INFRACFG_AO_GCE_SW_RST 97
#define MT8183_INFRACFG_AO_CLDMA_SW_RST 98
#define MT8183_INFRACFG_AO_TRNG_SW_RST 99
#define MT8183_INFRACFG_AO_AP_MD_CCIF_1_SW_RST 103
#define MT8183_INFRACFG_AO_AP_MD_CCIF_SW_RST 104
#define MT8183_INFRACFG_AO_I2C1_IMM_SW_RST 105
#define MT8183_INFRACFG_AO_I2C1_ARB_SW_RST 106
#define MT8183_INFRACFG_AO_I2C2_IMM_SW_RST 107
#define MT8183_INFRACFG_AO_I2C2_ARB_SW_RST 108
#define MT8183_INFRACFG_AO_I2C5_SW_RST 109
#define MT8183_INFRACFG_AO_I2C5_IMM_SW_RST 110
#define MT8183_INFRACFG_AO_I2C5_ARB_SW_RST 111
#define MT8183_INFRACFG_AO_SPI4_SW_RST 112
#define MT8183_INFRACFG_AO_SPI5_SW_RST 113
#define MT8183_INFRACFG_AO_INFRA2MFGAXI_CBIP_CLAS_SW_RST 114
#define MT8183_INFRACFG_AO_MFGAXI2INFRA_M0_CBIP_GLAS_OUT_SW_RST 115
#define MT8183_INFRACFG_AO_MFGAXI2INFRA_M1_CBIP_GLAS_OUT_SW_RST 116
#define MT8183_INFRACFG_AO_UFS_AES_SW_RST 117
#define MT8183_INFRACFG_AO_CCU_I2C_IRQ_SW_RST 118
#define MT8183_INFRACFG_AO_CCU_I2C_DMA_SW_RST 119
#define MT8183_INFRACFG_AO_I2C6_SW_RST 120
#define MT8183_INFRACFG_AO_CCU_GALS_SW_RST 121
#define MT8183_INFRACFG_AO_IPU_GALS_SW_RST 122
#define MT8183_INFRACFG_AO_CONN2AP_GALS_SW_RST 123
#define MT8183_INFRACFG_AO_AP_MD_CCIF2_SW_RST 124
#define MT8183_INFRACFG_AO_AP_MD_CCIF3_SW_RST 125
#define MT8183_INFRACFG_AO_I2C7_SW_RST 126
#define MT8183_INFRACFG_AO_I2C8_SW_RST 127
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */

38
include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 BayLibre, SAS.
* Author: Jerome Brunet <jbrunet@baylibre.com>
*
*/
#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H
#define _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H
#define AUD_RESET_PDM 0
#define AUD_RESET_TDMIN_A 1
#define AUD_RESET_TDMIN_B 2
#define AUD_RESET_TDMIN_C 3
#define AUD_RESET_TDMIN_LB 4
#define AUD_RESET_LOOPBACK 5
#define AUD_RESET_TODDR_A 6
#define AUD_RESET_TODDR_B 7
#define AUD_RESET_TODDR_C 8
#define AUD_RESET_FRDDR_A 9
#define AUD_RESET_FRDDR_B 10
#define AUD_RESET_FRDDR_C 11
#define AUD_RESET_TDMOUT_A 12
#define AUD_RESET_TDMOUT_B 13
#define AUD_RESET_TDMOUT_C 14
#define AUD_RESET_SPDIFOUT 15
#define AUD_RESET_SPDIFOUT_B 16
#define AUD_RESET_SPDIFIN 17
#define AUD_RESET_EQDRC 18
#define AUD_RESET_RESAMPLE 19
#define AUD_RESET_DDRARB 20
#define AUD_RESET_POWDET 21
#define AUD_RESET_TORAM 22
#define AUD_RESET_TOACODEC 23
#define AUD_RESET_TOHDMITX 24
#define AUD_RESET_CLKTREE 25
#endif