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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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sh: remove the broken SH_MPC1211 support
SH_MPC1211 has been marked as BROKEN for some time. Unless someone is working on reviving it now, I'd therefore suggest this patch to remove it. Signed-off-by: Adrian Bunk <[email protected]> Signed-off-by: Paul Mundt <[email protected]>
This commit is contained in:
Adrian Bunk
Paul Mundt
parent
2a6b8148c0
commit
f5f826c685
18 changed files with 2 additions and 1547 deletions
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@ -1,13 +0,0 @@
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#ifndef __ASM_SH_KEYBOARD_H
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#define __ASM_SH_KEYBOARD_H
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/*
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* $Id: keyboard.h,v 1.1.1.1 2001/10/15 20:45:09 mrbrown Exp $
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*/
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#include <linux/kd.h>
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#include <asm/machvec.h>
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#ifdef CONFIG_SH_MPC1211
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#include <asm/mpc1211/keyboard-mpc1211.h>
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#endif
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#endif
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@ -1,303 +0,0 @@
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/* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
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* linux/include/asm/dma.h: Defines for using and allocating dma channels.
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* Written by Hennus Bergman, 1992.
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* High DMA channel support & info by Hannu Savolainen
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* and John Boyd, Nov. 1992.
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*/
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#ifndef _ASM_MPC1211_DMA_H
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#define _ASM_MPC1211_DMA_H
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#include <linux/spinlock.h> /* And spinlocks */
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#include <asm/io.h> /* need byte IO */
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#include <linux/delay.h>
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#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
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#define dma_outb outb_p
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#else
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#define dma_outb outb
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#endif
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#define dma_inb inb
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/*
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* NOTES about DMA transfers:
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*
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* controller 1: channels 0-3, byte operations, ports 00-1F
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* controller 2: channels 4-7, word operations, ports C0-DF
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*
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* - ALL registers are 8 bits only, regardless of transfer size
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* - channel 4 is not used - cascades 1 into 2.
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* - channels 0-3 are byte - addresses/counts are for physical bytes
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* - channels 5-7 are word - addresses/counts are for physical words
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* - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
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* - transfer count loaded to registers is 1 less than actual count
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* - controller 2 offsets are all even (2x offsets for controller 1)
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* - page registers for 5-7 don't use data bit 0, represent 128K pages
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* - page registers for 0-3 use bit 0, represent 64K pages
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*
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* DMA transfers are limited to the lower 16MB of _physical_ memory.
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* Note that addresses loaded into registers must be _physical_ addresses,
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* not logical addresses (which may differ if paging is active).
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*
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* Address mapping for channels 0-3:
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*
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* A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
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* | ... | | ... | | ... |
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* | ... | | ... | | ... |
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* | ... | | ... | | ... |
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* P7 ... P0 A7 ... A0 A7 ... A0
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* | Page | Addr MSB | Addr LSB | (DMA registers)
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*
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* Address mapping for channels 5-7:
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*
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* A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
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* | ... | \ \ ... \ \ \ ... \ \
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* | ... | \ \ ... \ \ \ ... \ (not used)
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* | ... | \ \ ... \ \ \ ... \
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* P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
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* | Page | Addr MSB | Addr LSB | (DMA registers)
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*
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* Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
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* and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
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* the hardware level, so odd-byte transfers aren't possible).
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*
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* Transfer count (_not # bytes_) is limited to 64K, represented as actual
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* count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
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* and up to 128K bytes may be transferred on channels 5-7 in one operation.
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*
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*/
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#define MAX_DMA_CHANNELS 8
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/* The maximum address that we can perform a DMA transfer to on this platform */
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#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
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/* 8237 DMA controllers */
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#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
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#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
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/* DMA controller registers */
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#define DMA1_CMD_REG 0x08 /* command register (w) */
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#define DMA1_STAT_REG 0x08 /* status register (r) */
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#define DMA1_REQ_REG 0x09 /* request register (w) */
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#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
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#define DMA1_MODE_REG 0x0B /* mode register (w) */
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#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
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#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
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#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
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#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
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#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
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#define DMA2_CMD_REG 0xD0 /* command register (w) */
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#define DMA2_STAT_REG 0xD0 /* status register (r) */
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#define DMA2_REQ_REG 0xD2 /* request register (w) */
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#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
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#define DMA2_MODE_REG 0xD6 /* mode register (w) */
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#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
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#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
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#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
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#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
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#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
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#define DMA_ADDR_0 0x00 /* DMA address registers */
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#define DMA_ADDR_1 0x02
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#define DMA_ADDR_2 0x04
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#define DMA_ADDR_3 0x06
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#define DMA_ADDR_4 0xC0
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#define DMA_ADDR_5 0xC4
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#define DMA_ADDR_6 0xC8
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#define DMA_ADDR_7 0xCC
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#define DMA_CNT_0 0x01 /* DMA count registers */
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#define DMA_CNT_1 0x03
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#define DMA_CNT_2 0x05
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#define DMA_CNT_3 0x07
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#define DMA_CNT_4 0xC2
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#define DMA_CNT_5 0xC6
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#define DMA_CNT_6 0xCA
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#define DMA_CNT_7 0xCE
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#define DMA_PAGE_0 0x87 /* DMA page registers */
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#define DMA_PAGE_1 0x83
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#define DMA_PAGE_2 0x81
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#define DMA_PAGE_3 0x82
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#define DMA_PAGE_5 0x8B
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#define DMA_PAGE_6 0x89
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#define DMA_PAGE_7 0x8A
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#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
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#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
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#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
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#define DMA_AUTOINIT 0x10
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extern spinlock_t dma_spin_lock;
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static __inline__ unsigned long claim_dma_lock(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&dma_spin_lock, flags);
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return flags;
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}
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static __inline__ void release_dma_lock(unsigned long flags)
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{
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spin_unlock_irqrestore(&dma_spin_lock, flags);
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}
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/* enable/disable a specific DMA channel */
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static __inline__ void enable_dma(unsigned int dmanr)
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{
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if (dmanr<=3)
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dma_outb(dmanr, DMA1_MASK_REG);
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else
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dma_outb(dmanr & 3, DMA2_MASK_REG);
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}
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static __inline__ void disable_dma(unsigned int dmanr)
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{
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if (dmanr<=3)
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dma_outb(dmanr | 4, DMA1_MASK_REG);
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else
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dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
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}
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/* Clear the 'DMA Pointer Flip Flop'.
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* Write 0 for LSB/MSB, 1 for MSB/LSB access.
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* Use this once to initialize the FF to a known state.
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* After that, keep track of it. :-)
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* --- In order to do that, the DMA routines below should ---
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* --- only be used while holding the DMA lock ! ---
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*/
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static __inline__ void clear_dma_ff(unsigned int dmanr)
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{
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if (dmanr<=3)
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dma_outb(0, DMA1_CLEAR_FF_REG);
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else
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dma_outb(0, DMA2_CLEAR_FF_REG);
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}
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/* set mode (above) for a specific DMA channel */
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static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
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{
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if (dmanr<=3)
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dma_outb(mode | dmanr, DMA1_MODE_REG);
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else
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dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
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}
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/* Set only the page register bits of the transfer address.
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* This is used for successive transfers when we know the contents of
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* the lower 16 bits of the DMA current address register, but a 64k boundary
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* may have been crossed.
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*/
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static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
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{
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switch(dmanr) {
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case 0:
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dma_outb( pagenr & 0xff, DMA_PAGE_0);
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dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_0 + 0x400);
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break;
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case 1:
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dma_outb( pagenr & 0xff, DMA_PAGE_1);
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dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_1 + 0x400);
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break;
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case 2:
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dma_outb( pagenr & 0xff, DMA_PAGE_2);
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dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_2 + 0x400);
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break;
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case 3:
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dma_outb( pagenr & 0xff, DMA_PAGE_3);
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dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_3 + 0x400);
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break;
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case 5:
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dma_outb( pagenr & 0xfe, DMA_PAGE_5);
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dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_5 + 0x400);
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break;
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case 6:
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dma_outb( pagenr & 0xfe, DMA_PAGE_6);
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dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_6 + 0x400);
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break;
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case 7:
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dma_outb( pagenr & 0xfe, DMA_PAGE_7);
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dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_7 + 0x400);
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break;
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}
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}
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/* Set transfer address & page bits for specific DMA channel.
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* Assumes dma flipflop is clear.
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*/
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static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
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{
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set_dma_page(dmanr, a>>16);
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if (dmanr <= 3) {
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dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
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dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
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} else {
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dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
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dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
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}
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}
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/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
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* a specific DMA channel.
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* You must ensure the parameters are valid.
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* NOTE: from a manual: "the number of transfers is one more
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* than the initial word count"! This is taken into account.
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* Assumes dma flip-flop is clear.
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* NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
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*/
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static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
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{
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count--;
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if (dmanr <= 3) {
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dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
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dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
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} else {
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dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
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dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
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}
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}
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/* Get DMA residue count. After a DMA transfer, this
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* should return zero. Reading this while a DMA transfer is
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* still in progress will return unpredictable results.
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* If called before the channel has been used, it may return 1.
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* Otherwise, it returns the number of _bytes_ left to transfer.
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*
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* Assumes DMA flip-flop is clear.
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*/
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static __inline__ int get_dma_residue(unsigned int dmanr)
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{
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unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
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: ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
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/* using short to get 16-bit wrap around */
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unsigned short count;
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count = 1 + dma_inb(io_port);
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count += dma_inb(io_port) << 8;
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return (dmanr<=3)? count : (count<<1);
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}
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/* These are in kernel/dma.c: */
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extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
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extern void free_dma(unsigned int dmanr); /* release it again */
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/* From PCI */
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#ifdef CONFIG_PCI
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extern int isa_dma_bridge_buggy;
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#else
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#define isa_dma_bridge_buggy (0)
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#endif
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#endif /* _ASM_MPC1211_DMA_H */
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@ -1,22 +0,0 @@
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/*
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* include/asm-sh/mpc1211/io.h
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*
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* Copyright 2001 Saito.K & Jeanne
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*
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* IO functions for an Interface MPC-1211
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*/
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#ifndef _ASM_SH_IO_MPC1211_H
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#define _ASM_SH_IO_MPC1211_H
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#include <linux/time.h>
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extern int mpc1211_irq_demux(int irq);
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extern void init_mpc1211_IRQ(void);
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extern void heartbeat_mpc1211(void);
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extern void mpc1211_rtc_gettimeofday(struct timeval *tv);
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extern int mpc1211_rtc_settimeofday(const struct timeval *tv);
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#endif /* _ASM_SH_IO_MPC1211_H */
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/*
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* MPC1211 specific keybord definitions
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* Taken from the old asm-i386/keybord.h for PC/AT-style definitions
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* created 3 Nov 1996 by Geert Uytterhoeven.
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*/
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#ifdef __KERNEL__
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/kd.h>
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#include <linux/pm.h>
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#include <asm/io.h>
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#define KEYBOARD_IRQ 1
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#define DISABLE_KBD_DURING_INTERRUPTS 0
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extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
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extern int pckbd_getkeycode(unsigned int scancode);
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extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
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char raw_mode);
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extern char pckbd_unexpected_up(unsigned char keycode);
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extern void pckbd_leds(unsigned char leds);
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extern void pckbd_init_hw(void);
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extern int pckbd_pm_resume(struct pm_dev *, pm_request_t, void *);
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extern pm_callback pm_kbd_request_override;
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#define kbd_setkeycode pckbd_setkeycode
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#define kbd_getkeycode pckbd_getkeycode
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#define kbd_translate pckbd_translate
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#define kbd_unexpected_up pckbd_unexpected_up
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#define kbd_leds pckbd_leds
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#define kbd_init_hw pckbd_init_hw
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/* resource allocation */
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#define kbd_request_region()
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#define kbd_request_irq(handler) request_irq(KEYBOARD_IRQ, handler, 0, \
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"keyboard", NULL)
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/* How to access the keyboard macros on this platform. */
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#define kbd_read_input() inb(KBD_DATA_REG)
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#define kbd_read_status() inb(KBD_STATUS_REG)
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#define kbd_write_output(val) outb(val, KBD_DATA_REG)
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#define kbd_write_command(val) outb(val, KBD_CNTL_REG)
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/* Some stoneage hardware needs delays after some operations. */
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#define kbd_pause() do { } while(0)
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/*
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* Machine specific bits for the PS/2 driver
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*/
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#define AUX_IRQ 12
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#define aux_request_irq(hand, dev_id) \
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request_irq(AUX_IRQ, hand, IRQF_SHARED, "PS2 Mouse", dev_id)
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#define aux_free_irq(dev_id) free_irq(AUX_IRQ, dev_id)
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#endif /* __KERNEL__ */
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@ -1,200 +0,0 @@
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#ifndef __ASM_SH_M1543C_H
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#define __ASM_SH_M1543C_H
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/*
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* linux/include/asm-sh/m1543c.h
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* Copyright (C) 2001 Nobuhiro Sakawa
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* M1543C:PCI-ISA Bus Bridge with Super IO Chip support
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*
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* from
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*
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* linux/include/asm-sh/smc37c93x.h
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*
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* Copyright (C) 2000 Kazumoto Kojima
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*
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* SMSC 37C93x Super IO Chip support
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*/
|
||||
|
||||
/* Default base I/O address */
|
||||
#define FDC_PRIMARY_BASE 0x3f0
|
||||
#define IDE1_PRIMARY_BASE 0x1f0
|
||||
#define IDE1_SECONDARY_BASE 0x170
|
||||
#define PARPORT_PRIMARY_BASE 0x378
|
||||
#define COM1_PRIMARY_BASE 0x2f8
|
||||
#define COM2_PRIMARY_BASE 0x3f8
|
||||
#define COM3_PRIMARY_BASE 0x3e8
|
||||
#define RTC_PRIMARY_BASE 0x070
|
||||
#define KBC_PRIMARY_BASE 0x060
|
||||
#define AUXIO_PRIMARY_BASE 0x000 /* XXX */
|
||||
#define I8259_M_CR 0x20
|
||||
#define I8259_M_MR 0x21
|
||||
#define I8259_S_CR 0xa0
|
||||
#define I8259_S_MR 0xa1
|
||||
|
||||
/* Logical device number */
|
||||
#define LDN_FDC 0
|
||||
#define LDN_IDE1 1
|
||||
#define LDN_IDE2 2
|
||||
#define LDN_PARPORT 3
|
||||
#define LDN_COM1 4
|
||||
#define LDN_COM2 5
|
||||
#define LDN_COM3 11
|
||||
#define LDN_RTC 6
|
||||
#define LDN_KBC 7
|
||||
|
||||
/* Configuration port and key */
|
||||
#define CONFIG_PORT 0x3f0
|
||||
#define INDEX_PORT CONFIG_PORT
|
||||
#define DATA_PORT 0x3f1
|
||||
#define CONFIG_ENTER1 0x51
|
||||
#define CONFIG_ENTER2 0x23
|
||||
#define CONFIG_EXIT 0xbb
|
||||
|
||||
/* Configuration index */
|
||||
#define CURRENT_LDN_INDEX 0x07
|
||||
#define POWER_CONTROL_INDEX 0x22
|
||||
#define ACTIVATE_INDEX 0x30
|
||||
#define IO_BASE_HI_INDEX 0x60
|
||||
#define IO_BASE_LO_INDEX 0x61
|
||||
#define IRQ_SELECT_INDEX 0x70
|
||||
#define PS2_IRQ_INDEX 0x72
|
||||
#define DMA_SELECT_INDEX 0x74
|
||||
|
||||
/* UART stuff. Only for debugging. */
|
||||
/* UART Register */
|
||||
|
||||
#define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */
|
||||
#define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */
|
||||
#define UART_IER 0x2 /* Interrupt Enable Register */
|
||||
#define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */
|
||||
#define UART_FCR 0x4 /* FIFO Control Register (Write Only) */
|
||||
#define UART_LCR 0x6 /* Line Control Register */
|
||||
#define UART_MCR 0x8 /* MODEM Control Register */
|
||||
#define UART_LSR 0xa /* Line Status Register */
|
||||
#define UART_MSR 0xc /* MODEM Status Register */
|
||||
#define UART_SCR 0xe /* Scratch Register */
|
||||
#define UART_DLL 0x0 /* Divisor Latch (LS) */
|
||||
#define UART_DLM 0x2 /* Divisor Latch (MS) */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef struct uart_reg {
|
||||
volatile __u16 rbr;
|
||||
volatile __u16 ier;
|
||||
volatile __u16 iir;
|
||||
volatile __u16 lcr;
|
||||
volatile __u16 mcr;
|
||||
volatile __u16 lsr;
|
||||
volatile __u16 msr;
|
||||
volatile __u16 scr;
|
||||
} uart_reg;
|
||||
#endif /* ! __ASSEMBLY__ */
|
||||
|
||||
/* Alias for Write Only Register */
|
||||
|
||||
#define thr rbr
|
||||
#define tcr iir
|
||||
|
||||
/* Alias for Divisor Latch Register */
|
||||
|
||||
#define dll rbr
|
||||
#define dlm ier
|
||||
#define fcr iir
|
||||
|
||||
/* Interrupt Enable Register */
|
||||
|
||||
#define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */
|
||||
#define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */
|
||||
#define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */
|
||||
#define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */
|
||||
|
||||
/* Interrupt Ident Register */
|
||||
|
||||
#define IIR_IP 0x0100 /* "0" if Interrupt Pending */
|
||||
#define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */
|
||||
#define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */
|
||||
#define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */
|
||||
#define IIR_FIFO 0xc000 /* FIFOs enabled */
|
||||
|
||||
/* FIFO Control Register */
|
||||
|
||||
#define FCR_FEN 0x0100 /* FIFO enable */
|
||||
#define FCR_RFRES 0x0200 /* Receiver FIFO reset */
|
||||
#define FCR_TFRES 0x0400 /* Transmitter FIFO reset */
|
||||
#define FCR_DMA 0x0800 /* DMA mode select */
|
||||
#define FCR_RTL 0x4000 /* Receiver triger (LSB) */
|
||||
#define FCR_RTM 0x8000 /* Receiver triger (MSB) */
|
||||
|
||||
/* Line Control Register */
|
||||
|
||||
#define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */
|
||||
#define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */
|
||||
#define LCR_STB 0x0400 /* Number of Stop Bits */
|
||||
#define LCR_PEN 0x0800 /* Parity Enable */
|
||||
#define LCR_EPS 0x1000 /* Even Parity Select */
|
||||
#define LCR_SP 0x2000 /* Stick Parity */
|
||||
#define LCR_SB 0x4000 /* Set Break */
|
||||
#define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */
|
||||
|
||||
/* MODEM Control Register */
|
||||
|
||||
#define MCR_DTR 0x0100 /* Data Terminal Ready */
|
||||
#define MCR_RTS 0x0200 /* Request to Send */
|
||||
#define MCR_OUT1 0x0400 /* Out 1 */
|
||||
#define MCR_IRQEN 0x0800 /* IRQ Enable */
|
||||
#define MCR_LOOP 0x1000 /* Loop */
|
||||
|
||||
/* Line Status Register */
|
||||
|
||||
#define LSR_DR 0x0100 /* Data Ready */
|
||||
#define LSR_OE 0x0200 /* Overrun Error */
|
||||
#define LSR_PE 0x0400 /* Parity Error */
|
||||
#define LSR_FE 0x0800 /* Framing Error */
|
||||
#define LSR_BI 0x1000 /* Break Interrupt */
|
||||
#define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */
|
||||
#define LSR_TEMT 0x4000 /* Transmitter Empty */
|
||||
#define LSR_FIFOE 0x8000 /* Receiver FIFO error */
|
||||
|
||||
/* MODEM Status Register */
|
||||
|
||||
#define MSR_DCTS 0x0100 /* Delta Clear to Send */
|
||||
#define MSR_DDSR 0x0200 /* Delta Data Set Ready */
|
||||
#define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */
|
||||
#define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */
|
||||
#define MSR_CTS 0x1000 /* Clear to Send */
|
||||
#define MSR_DSR 0x2000 /* Data Set Ready */
|
||||
#define MSR_RI 0x4000 /* Ring Indicator */
|
||||
#define MSR_DCD 0x8000 /* Data Carrier Detect */
|
||||
|
||||
/* Baud Rate Divisor */
|
||||
|
||||
#define UART_CLK (1843200) /* 1.8432 MHz */
|
||||
#define UART_BAUD(x) (UART_CLK / (16 * (x)))
|
||||
|
||||
/* RTC register definition */
|
||||
#define RTC_SECONDS 0
|
||||
#define RTC_SECONDS_ALARM 1
|
||||
#define RTC_MINUTES 2
|
||||
#define RTC_MINUTES_ALARM 3
|
||||
#define RTC_HOURS 4
|
||||
#define RTC_HOURS_ALARM 5
|
||||
#define RTC_DAY_OF_WEEK 6
|
||||
#define RTC_DAY_OF_MONTH 7
|
||||
#define RTC_MONTH 8
|
||||
#define RTC_YEAR 9
|
||||
#define RTC_FREQ_SELECT 10
|
||||
# define RTC_UIP 0x80
|
||||
# define RTC_DIV_CTL 0x70
|
||||
/* This RTC can work under 32.768KHz clock only. */
|
||||
# define RTC_OSC_ENABLE 0x20
|
||||
# define RTC_OSC_DISABLE 0x00
|
||||
#define RTC_CONTROL 11
|
||||
# define RTC_SET 0x80
|
||||
# define RTC_PIE 0x40
|
||||
# define RTC_AIE 0x20
|
||||
# define RTC_UIE 0x10
|
||||
# define RTC_SQWE 0x08
|
||||
# define RTC_DM_BINARY 0x04
|
||||
# define RTC_24H 0x02
|
||||
# define RTC_DST_EN 0x01
|
||||
|
||||
#endif /* __ASM_SH_M1543C_H */
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/*
|
||||
* MPC1211 uses PC/AT style RTC definitions.
|
||||
*/
|
||||
#include <asm-x86/mc146818rtc_32.h>
|
||||
|
||||
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
#ifndef __ASM_SH_MPC1211_H
|
||||
#define __ASM_SH_MPC1211_H
|
||||
|
||||
/*
|
||||
* linux/include/asm-sh/mpc1211.h
|
||||
*
|
||||
* Copyright (C) 2001 Saito.K & Jeanne
|
||||
*
|
||||
* Interface MPC-1211 support
|
||||
*/
|
||||
|
||||
#define PA_PCI_IO (0xa4000000) /* PCI I/O space */
|
||||
#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */
|
||||
|
||||
#define PCIPAR (0xa4000cf8) /* PCI Config address */
|
||||
#define PCIPDR (0xa4000cfc) /* PCI Config data */
|
||||
|
||||
#endif /* __ASM_SH_MPC1211_H */
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
/*
|
||||
* Low-Level PCI Support for MPC-1211
|
||||
*
|
||||
* (c) 2002 Saito.K & Jeanne
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _PCI_MPC1211_H_
|
||||
#define _PCI_MPC1211_H_
|
||||
|
||||
#include <linux/pci.h>
|
||||
|
||||
/* set debug level 4=verbose...1=terse */
|
||||
//#define DEBUG_PCI 3
|
||||
#undef DEBUG_PCI
|
||||
|
||||
#ifdef DEBUG_PCI
|
||||
#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); }
|
||||
#else
|
||||
#define PCIDBG(n, x...)
|
||||
#endif
|
||||
|
||||
/* startup values */
|
||||
#define PCI_PROBE_BIOS 1
|
||||
#define PCI_PROBE_CONF1 2
|
||||
#define PCI_PROBE_CONF2 4
|
||||
#define PCI_NO_CHECKS 0x400
|
||||
#define PCI_ASSIGN_ROMS 0x1000
|
||||
#define PCI_BIOS_IRQ_SCAN 0x2000
|
||||
|
||||
/* MPC-1211 Specific Values */
|
||||
#define PCIPAR (0xa4000cf8) /* PCI Config address */
|
||||
#define PCIPDR (0xa4000cfc) /* PCI Config data */
|
||||
|
||||
#define PA_PCI_IO (0xa4000000) /* PCI I/O space */
|
||||
#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */
|
||||
|
||||
#endif /* _PCI_MPC1211_H_ */
|
||||
Loading…
Reference in a new issue