From f65f53d3bd359bb1c142d9f14e11ef7e958403a9 Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Fri, 28 May 2021 13:31:18 -0700 Subject: [PATCH] clk: qcom: clk-alpha-pll: Add clk_alpha_pll_lucid_5lpe_sdx_cpu_ops The lucid_5lpe PLL used for the CPU on SDX targets uses a custom mechanism to assert the latch. Add ops that can be used for this. Change-Id: I24f8e3db2b908e34e4d0560841f1f5fdcfd215af Signed-off-by: Mike Tipton --- drivers/clk/qcom/clk-alpha-pll.c | 80 ++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 3 +- 2 files changed, 82 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index f81ef5d61313..e40f344609f8 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -276,6 +276,12 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) #define LUCID_EVO_PLL_CAL_L_VAL_MASK GENMASK(31, 16) +/* + * The lucid_5lpe CPU PLL on SDX targets overloaded this field. Reading it + * returns PCAL_DONE and writing it asserts the latch. + */ +#define LUCID_5LPE_SDX_CPU_LATCH_INPUT LUCID_5LPE_PCAL_DONE + /* ZONDA PLL specific offsets */ #define ZONDA_PLL_OUT_MASK 0xF #define ZONDA_STAY_IN_CFA BIT(16) @@ -3190,6 +3196,61 @@ static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static int alpha_pll_lucid_5lpe_sdx_cpu_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long prate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + unsigned long rrate; + u32 regval, l; + u64 a; + int ret; + + rrate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_16BIT_WIDTH); + + /* + * Due to a limited number of bits for fractional rate programming, the + * rounded up rate could be marginally higher than the requested rate. + */ + if (rrate > (rate + PLL_OUT_RATE_MARGIN) || rrate < rate) { + pr_err("Call set rate on the PLL with rounded rates!\n"); + return -EINVAL; + } + + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); + + /* Latch the PLL input */ + ret = regmap_write_bits(pll->clkr.regmap, PLL_MODE(pll), + LUCID_5LPE_SDX_CPU_LATCH_INPUT, + LUCID_5LPE_SDX_CPU_LATCH_INPUT); + if (ret) + return ret; + + /* Wait for 2 reference cycles before checking the ACK bit. */ + udelay(1); + regmap_read(pll->clkr.regmap, PLL_MODE(pll), ®val); + if (!(regval & LUCID_5LPE_ALPHA_PLL_ACK_LATCH)) { + WARN_CLK(&pll->clkr.hw, 1, + "PLL latch failed. Output may be unstable!\n"); + return -EINVAL; + } + + /* Return the latch input to 0 */ + ret = regmap_write_bits(pll->clkr.regmap, PLL_MODE(pll), + LUCID_5LPE_SDX_CPU_LATCH_INPUT, 0); + if (ret) + return ret; + + if (clk_hw_is_enabled(hw)) { + ret = wait_for_pll_enable_lock(pll); + if (ret) + return ret; + } + + return 0; +} + static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { @@ -3331,6 +3392,25 @@ const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { }; EXPORT_SYMBOL(clk_alpha_pll_lucid_5lpe_ops); +const struct clk_ops clk_alpha_pll_lucid_5lpe_sdx_cpu_ops = { + .prepare = alpha_pll_lucid_5lpe_prepare, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, + .enable = alpha_pll_lucid_5lpe_enable, + .disable = alpha_pll_lucid_5lpe_disable, + .is_enabled = alpha_pll_lucid_is_enabled, + .recalc_rate = alpha_pll_lucid_recalc_rate, + .round_rate = clk_alpha_pll_round_rate, + .set_rate = alpha_pll_lucid_5lpe_sdx_cpu_set_rate, + .debug_init = clk_common_debug_init, + .init = clk_lucid_pll_init, +#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG + .list_rate_vdd_level = clk_list_rate_vdd_level, +#endif +}; +EXPORT_SYMBOL(clk_alpha_pll_lucid_5lpe_sdx_cpu_ops); + const struct clk_ops clk_alpha_pll_fixed_lucid_ops = { .prepare = clk_prepare_regmap, .unprepare = clk_unprepare_regmap, diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index d5791e9cc4bf..d5f1ab60d6d1 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2015-2016, 2018-2020 The Linux Foundation. + * Copyright (c) 2015-2016, 2018-2021 The Linux Foundation. * All rights reserved. */ @@ -173,6 +173,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_zonda_ops; extern const struct clk_ops clk_alpha_pll_zonda_5lpe_ops; extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops; +extern const struct clk_ops clk_alpha_pll_lucid_5lpe_sdx_cpu_ops; extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops; extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; extern const struct clk_ops clk_alpha_pll_slew_ops;