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Amlogic clock driver updates for 4.13
* Expose more i2s and spdif output clocks * Expose EE uart and SPICC gate clocks * Remove cpu_clk from to gxbb * Mark clk81 as critical on gxbb * Add CEC EE clocks -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJZMYA7AAoJEAFRo5MEFpTROkYQAIil0GjmG8azaiGXFWZ3LMf1 NupLsoH6Xd3nBnUmFR0DIHcH8ZadK5Io0+hWSVG0xopJzQS7+HWr/CfgQzdSiAa1 VDRSBZcoEmTBgiMkXfzN56HgUW1fz/bkQ2vZavQFsRJznkH2/kR09uL+/4BAY41k v4uYZwXLbEFfYEytFrHzppV43W2CnaMN1EH7GpKUvP3VldxpCt0yYAQZFS7k2wyJ If44bKN7sGma8g4IxrcrJ3AnpvE+OyLQAYgMyC1jm5WdRyEfWjqMNj54YL4cyIpl x6v+38oB5y39g7/k+YCvCugoY25DnVcdzCdtkAY8rWfoStOl9R67CVKshEIfG9WN WfRFLGBoC5RINvMEffjWSGPaGms1Cuk0UNWBOFNGzjwbc6Gw3OYZ4oXq4oSz8vby /GZcogEocizX343id/vX/6WZWz2Pp2hPzFi3OrqIB0xb2jrTFxZ2zqYOeEp/ChCx 5HHVOwfrkKTEw6vvGre7VcIBipZ/MYoTWVUO86cVOpj+QuK2wigsTjTQWU0dVh2w JOOGfk+3nrLoKzPpRLHdicc3FYv038RJcV35UqPOVmOhUh7+lGkRBTgEZunLXJI4 6qLmT49OFgSqLtx4u2R92xIdZYRGq5ysmIutUkmw69quWcfytsj9rZALp+2TWf8i 02pZYwcKJbrwHwK+Eqkk =8rsv -----END PGP SIGNATURE----- Merge tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson into clk-next Pull Amlogic clock driver updates from Jerome Brunet: * Expose more i2s and spdif output clocks * Expose EE uart and SPICC gate clocks * Remove cpu_clk from to gxbb * Mark clk81 as critical on gxbb * Add CEC EE clocks * tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson: clk: meson-gxbb: Add EE 32K Clock for CEC clk: gxbb: remove CLK_IGNORE_UNUSED from clk81 clk: meson: meson8b: mark clk81 as critical clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driver clk: meson-gxbb: un-export the CPU clock clk: meson-gxbb: expose UART clocks clk: meson-gxbb: expose SPICC gate clk: meson-gxbb: expose spdif master clock clk: meson-gxbb: expose i2s master clock clk: meson-gxbb: expose spdif clock gates
This commit is contained in:
commit
f6b3130919
4 changed files with 82 additions and 75 deletions
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@ -5,7 +5,6 @@
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#ifndef __GXBB_CLKC_H
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#define __GXBB_CLKC_H
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#define CLKID_CPUCLK 1
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#define CLKID_HDMI_PLL 2
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#define CLKID_FCLK_DIV2 4
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#define CLKID_FCLK_DIV3 5
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@ -13,24 +12,30 @@
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#define CLKID_GP0_PLL 9
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#define CLKID_CLK81 12
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#define CLKID_MPLL2 15
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#define CLKID_SPICC 21
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#define CLKID_I2C 22
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#define CLKID_SAR_ADC 23
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#define CLKID_RNG0 25
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#define CLKID_UART0 26
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#define CLKID_SPI 34
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#define CLKID_ETH 36
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#define CLKID_AIU_GLUE 38
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#define CLKID_IEC958 39
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#define CLKID_I2S_OUT 40
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#define CLKID_MIXER_IFACE 44
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#define CLKID_AIU 47
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#define CLKID_UART1 48
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#define CLKID_USB0 50
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#define CLKID_USB1 51
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#define CLKID_USB 55
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#define CLKID_HDMI_PCLK 63
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#define CLKID_USB1_DDR_BRIDGE 64
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#define CLKID_USB0_DDR_BRIDGE 65
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#define CLKID_UART2 68
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#define CLKID_SANA 69
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#define CLKID_GCLK_VENCI_INT0 77
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#define CLKID_AOCLK_GATE 80
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#define CLKID_IEC958_GATE 81
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#define CLKID_AO_I2C 93
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#define CLKID_SD_EMMC_A 94
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#define CLKID_SD_EMMC_B 95
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#define CLKID_MALI_1_SEL 103
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#define CLKID_MALI_1 105
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#define CLKID_MALI 106
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#define CLKID_CTS_AMCLK 107
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#define CLKID_CTS_MCLK_I958 110
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#define CLKID_CTS_I958 113
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#endif /* __GXBB_CLKC_H */
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