From bab76a95c039438218a8aea6ef2cdba8b64af6f5 Mon Sep 17 00:00:00 2001 From: Can Guo Date: Wed, 12 May 2021 07:59:17 +0800 Subject: [PATCH 1/2] msm: ep-pcie: Allow device enter L1 right after BME is set Allow device enter L1, i.e. clear PCIE_0_PCIE_PARF_PM_CTRL[REQ_NOT_ENTR_L1] once we find out BME is set. Change-Id: I8aca816446a286d02ef51724d157cb7c75057250 Signed-off-by: Can Guo --- drivers/platform/msm/ep_pcie/ep_pcie_core.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c index 4d524e8e47bf..74009b75ae91 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c @@ -657,10 +657,6 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) PCIE20_LINK_CONTROL2_LINK_STATUS2, 0xf, dev->link_speed); - EP_PCIE_DBG2(dev, "PCIe V%d: Allow L1 after D3_COLD->D0\n", - dev->rev); - ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0); - EP_PCIE_DBG2(dev, "PCIe V%d: Clear disconn_req after D3_COLD\n", dev->rev); ep_pcie_write_reg_field(dev->tcsr_perst_en, @@ -1976,6 +1972,11 @@ checkbme: dev->rev, retries, BME_TIMEOUT_US_MIN * retries / 1000); ep_pcie_enumeration_complete(dev); + + EP_PCIE_DBG2(dev, "PCIe V%d: Allow L1 after BME is set\n", + dev->rev); + ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0); + /* expose BAR to user space to identify modem */ ep_pcie_bar0_address = readl_relaxed(dev->dm_core + PCIE20_BAR0); @@ -2149,6 +2150,10 @@ static irqreturn_t ep_pcie_handle_bme_irq(int irq, void *data) dev->rev); ep_pcie_notify_event(dev, EP_PCIE_EVENT_LINKUP); } + + EP_PCIE_DBG2(dev, "PCIe V%d: Allow L1 after BME is set\n", + dev->rev); + ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0); } else { EP_PCIE_DBG(dev, "PCIe V%d:BME is still disabled\n", dev->rev); From c150d993f3e487cf1a3ebf3ac38ecac62f3ec488 Mon Sep 17 00:00:00 2001 From: Can Guo Date: Tue, 11 May 2021 12:24:48 +0800 Subject: [PATCH 2/2] msm: ep-pcie: Correct two CAP reg offsets Correct the offsets of L1SUB_CAPABILITY_REG and L1SUB_CONTROL1_REG. Change-Id: I6130a7eab50d85e34d87c28bde3a48c058ee9eee Signed-off-by: Can Guo --- drivers/platform/msm/ep_pcie/ep_pcie_com.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_com.h b/drivers/platform/msm/ep_pcie/ep_pcie_com.h index a9ad61a9f490..db676c486ea3 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_com.h +++ b/drivers/platform/msm/ep_pcie/ep_pcie_com.h @@ -105,8 +105,8 @@ #define PCIE20_CAP_LINKCTRLSTATUS 0x80 #define PCIE20_DEVICE_CONTROL2_STATUS2 0x98 #define PCIE20_LINK_CONTROL2_LINK_STATUS2 0xA0 -#define PCIE20_L1SUB_CAPABILITY 0x154 -#define PCIE20_L1SUB_CONTROL1 0x158 +#define PCIE20_L1SUB_CAPABILITY 0x234 +#define PCIE20_L1SUB_CONTROL1 0x238 #define PCIE20_BUS_DISCONNECT_STATUS 0x68c #define PCIE20_ACK_F_ASPM_CTRL_REG 0x70C #define PCIE20_MASK_ACK_N_FTS 0xff00