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Merge tag 'LA.UM.9.14.r1-20500.01-LAHAINA.QSSI12.0' of https://git.codelinaro.org/clo/la/platform/vendor/qcom-opensource/wlan/fw-api into android12-5.4-lahaina
"LA.UM.9.14.r1-20500.01-LAHAINA.QSSI12.0" * tag 'LA.UM.9.14.r1-20500.01-LAHAINA.QSSI12.0' of https://git.codelinaro.org/clo/la/platform/vendor/qcom-opensource/wlan/fw-api: fw-api: CL 19061926 - update fw common interface files fw-api: CL 19061219 - update fw common interface files fw-api: CL 19047183 - update fw common interface files fw-api: CL 19029549 - update fw common interface files fw-api: CL 19024619 - update fw common interface files fw-api: CL 19024615 - update fw common interface files fw-api: CL 19010813 - update fw common interface files fw-api: CL 18998456 - update fw common interface files fw-api: CL 18987039 - update fw common interface files fw-api: CL 18966584 - update fw common interface files fw-api: CL 18946469 - update fw common interface files fw-api: CL 18946444 - update fw common interface files fw-api: CL 18916860 - update fw common interface files fw-api: Add headers for qcn9224 v2 fw-api: CL 18860032 - update fw common interface files fw-api: CL 18844589 - update fw common interface files fw-api: CL 18844583 - update fw common interface files fw-api: CL 18827872 - update fw common interface files fw-api: CL 18809954 - update fw common interface files fw-api: CL 18774949 - update fw common interface files fw-api: CL 18757174 - update fw common interface files fw-api: CL 18739769 - update fw common interface files fw-api: CL 18709242 - update fw common interface files fw-api: CL 18685702 - update fw common interface files fw-api: CL 18643854 - update fw common interface files fw-api: Add missing header for qca8074V2 fw-api: CL 18584219 - update fw common interface files fw-api: CL 18582357 - update fw common interface files fw-api: CL 18549173 - update fw common interface files fw-api: CL 18544227 - update fw common interface files fw-api: CL 18528502 - update fw common interface files fw-api: CL 18520590 - update fw common interface files fw-api: CL 18520582 - update fw common interface files fw-api: CL 18514323 - update fw common interface files fw-api: CL 18495064 - update fw common interface files fw-api: CL 18480658 - update fw common interface files fw-api: CL 18479583 - update fw common interface files fw-api: CL 18472328 - update fw common interface files fw-api: CL 18469088 - update fw common interface files fw-api: CL 18457221 - update fw common interface files fw-api: CL 18457215 - update fw common interface files fw-api: Fix compilation issue for tx monitor fw-api: CL 18412145 - update fw common interface files fw-api: CL 18399677 - update fw common interface files fw-api: CL 18347006 - update fw common interface files fw-api: CL 18311866 - update fw common interface files fw-api: CL 18291512 - update fw common interface files fw-api: CL 18227240 - update fw common interface files fw-api: CL 18225673 - update fw common interface files fw-api: CL 18211442 - update fw common interface files fw-api: CL 18197955 - update fw common interface files fw-api: CL 18177396 - update fw common interface files fw-api: CL 18177389 - update fw common interface files fw-api: CL 18173549 - update fw common interface files fw-api: add rx_reo_queue_1k.h file for 1K BA window support fw-api: CL 18137973 - update fw common interface files fw-api: CL 18119950 - update fw common interface files fw-api: CL 18116081 - update fw common interface files fw-api: CL 18116079 - update fw common interface files fw-api: CL 18101507 - update fw common interface files fw-api: CL 18098896 - update fw common interface files fw-api: CL 18096193 - update fw common interface files fw-api: CL 18082017 - update fw common interface files fw-api: CL 18082015 - update fw common interface files fw-api: CL 18037073 - update fw common interface files fw-api: CL 18037070 - update fw common interface files fw-api: CL 18000081 - update fw common interface files fw-api: CL 17986784 - update fw common interface files fw-api: CL 17986781 - update fw common interface files fw-api: CL 17969296 - update fw common interface files Change-Id: I967b0555f7991ed6fe351b015cda196173cc39a1
This commit is contained in:
Michael Bestas
commit
f7866a8e2f
423 changed files with 157615 additions and 28 deletions
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2012, 2014-2017, 2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
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*
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@ -58,7 +59,8 @@ typedef enum {
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#define WMI_CONTROL_SVC_WMAC1 MAKE_SERVICE_ID(WMI_SERVICE_GROUP,5)
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#define WMI_CONTROL_SVC_WMAC2 MAKE_SERVICE_ID(WMI_SERVICE_GROUP,6)
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#define WMI_CONTROL_DIAG_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,7)
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#define WMI_MAX_SERVICES 8
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#define WMI_CONTROL_DBR_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,8)
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#define WMI_MAX_SERVICES 9
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#define NMI_CONTROL_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,0)
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#define NMI_DATA_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,1)
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@ -230,9 +230,13 @@
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* 3.103 Add HTT_T2H_SAWF_MSDUQ_INFO_IND defs.
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* 3.104 Add mgmt/ctrl/data specs in rx ring cfg.
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* 3.105 Add HTT_H2T STREAMING_STATS_REQ + HTT_T2H STREAMING_STATS_IND defs.
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* 3.106 Add HTT_T2H_PPDU_ID_FMT_IND def.
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* 3.107 Add traffic_end_indication bitfield in htt_tx_msdu_desc_ext2_t.
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* 3.108 Add HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP def.
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* 3.109 Add HTT_T2H RX_ADDBA_EXTN,RX_DELBA_EXTN defs.
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*/
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#define HTT_CURRENT_VERSION_MAJOR 3
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#define HTT_CURRENT_VERSION_MINOR 105
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#define HTT_CURRENT_VERSION_MINOR 109
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#define HTT_NUM_TX_FRAG_DESC 1024
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@ -741,6 +745,15 @@ typedef enum {
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HTT_STATS_TXBF_OFDMA_BE_BRP_STATS_TAG = 153, /* htt_txbf_ofdma_be_brp_stats_tlv */
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HTT_STATS_TXBF_OFDMA_BE_STEER_STATS_TAG = 154, /* htt_txbf_ofdma_be_steer_stats_tlv */
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HTT_STATS_DMAC_RESET_STATS_TAG = 155, /* htt_dmac_reset_stats_tlv */
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HTT_STATS_RX_PDEV_BE_UL_OFDMA_USER_STATS_TAG = 156, /* htt_rx_pdev_be_ul_ofdma_user_stats_tlv */
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HTT_STATS_PHY_TPC_STATS_TAG = 157, /* htt_phy_tpc_stats_tlv */
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HTT_STATS_PDEV_PUNCTURE_STATS_TAG = 158, /* htt_pdev_puncture_stats_tlv */
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HTT_STATS_ML_PEER_DETAILS_TAG = 159, /* htt_ml_peer_details_tlv */
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HTT_STATS_ML_PEER_EXT_DETAILS_TAG = 160, /* htt_ml_peer_ext_details_tlv */
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HTT_STATS_ML_LINK_INFO_DETAILS_TAG = 161, /* htt_ml_link_info_tlv */
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HTT_STATS_TX_PDEV_PPDU_DUR_TAG = 162, /* htt_tx_pdev_ppdu_dur_stats_tlv */
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HTT_STATS_RX_PDEV_PPDU_DUR_TAG = 163, /* htt_rx_pdev_ppdu_dur_stats_tlv */
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HTT_STATS_ODD_PDEV_MANDATORY_TAG = 164, /* htt_odd_mandatory_pdev_stats_tlv */
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HTT_STATS_MAX_TAG,
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@ -809,6 +822,7 @@ enum htt_h2t_msg_type {
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HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ = 0x1e,
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HTT_H2T_MSG_TYPE_MSI_SETUP = 0x1f,
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HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ = 0x20,
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HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP = 0x21,
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/* keep this last */
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HTT_H2T_NUM_MSGS
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@ -1971,7 +1985,8 @@ PREPACK struct htt_tx_msdu_desc_ext2_t {
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* with valid information.
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*/
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is_host_opaque_valid : 1,
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rsvd0 : 29;
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traffic_end_indication: 1,
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rsvd0 : 28;
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/* DWORD 6 : Host opaque cookie for special frames */
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A_UINT32 host_opaque_cookie : 16, /* see is_host_opaque_valid */
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@ -5170,6 +5185,8 @@ enum htt_srng_ring_id {
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HTT_TX_MON_MON2HOST_DEST_RING, /* Used by monitor to fill status buffers and provide to host */
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HTT_RX_MON_HOST2MON_BUF_RING, /* Status buffers and Packet buffers are provided by host */
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HTT_RX_MON_MON2HOST_DEST_RING, /* Used by monitor to fill status buffers and provide to host */
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HTT_LPASS_TO_FW_RXBUF_RING, /* new LPASS to FW refill ring to recycle rx buffers */
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HTT_HOST3_TO_FW_RXBUF_RING, /* used by host for EasyMesh feature */
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/* Add Other SRING which can't be directly configured by host software above this line */
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};
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@ -9186,7 +9203,10 @@ PREPACK struct htt_h2t_host_paddr_size_entry_t {
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A_UINT32 physical_address_hi;
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} POSTPACK;
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#define HTT_H2T_HOST_PADDR_SIZE_ENTRY_SIZE (sizeof(struct htt_h2t_host_paddr_size_entry_t))
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#define HTT_H2T_HOST_PADDR_SIZE_ENTRY_SIZE \
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(sizeof(struct htt_h2t_host_paddr_size_entry_t))
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#define HTT_H2T_HOST_PADDR_SIZE_ENTRY_DWORDS \
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(HTT_H2T_HOST_PADDR_SIZE_ENTRY_SIZE >> 2)
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#define HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_M 0x0000FF00
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#define HTT_H2T_HOST_PADDR_SIZE_NUM_ENTRIES_S 8
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@ -9600,6 +9620,237 @@ PREPACK struct htt_h2t_sawf_def_queues_map_report_req {
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((word1) |= ((_val) << HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ_EXISTING_TIDS_ONLY_S)); \
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} while (0)
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/**
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* @brief Format of shared memory between Host and Target
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* for UMAC hang recovery feature messaging.
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* @details
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* This is shared memory between Host and Target allocated
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* and used in chips where UMAC hang recovery feature is supported.
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* If target sets a bit in t2h_msg (provided it's valid bit offset)
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* then host interprets it as a new message from target.
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* Host clears that particular read bit in t2h_msg after each read
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* operation. It is vice versa for h2t_msg. At any given point
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* of time there is expected to be only one bit set
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* either in t2h_msg or h2t_msg (referring to valid bit offset).
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*
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* The message is interpreted as follows:
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* dword0 - b'0:31 - magic_num: Magic number for the shared memory region
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* added for debuggability purpose.
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* dword1 - b'0 - do_pre_reset
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* b'1 - do_post_reset_start
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* b'2 - do_post_reset_complete
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* b'3:31 - rsvd_t2h
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* dword2 - b'0 - pre_reset_done
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* b'1 - post_reset_start_done
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* b'2 - post_reset_complete_done
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* b'3:31 - rsvd_h2t
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*/
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PREPACK typedef struct {
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/** Magic number added for debuggability. */
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A_UINT32 magic_num;
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union {
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/*
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* BIT [0] :- T2H msg to do pre-reset
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* BIT [1] :- T2H msg to do post-reset start
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* BIT [2] :- T2H msg to do post-reset complete
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* BIT [31 : 3] :- reserved
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*/
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A_UINT32 t2h_msg;
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struct {
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A_UINT32 do_pre_reset : 1, /* BIT [0] */
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do_post_reset_start : 1, /* BIT [1] */
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do_post_reset_complete : 1, /* BIT [2] */
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rsvd_t2h : 29; /* BIT [31 : 3] */
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};
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};
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union {
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/*
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* BIT [0] :- H2T msg to send pre-reset done
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* BIT [1] :- H2T msg to send post-reset start done
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* BIT [2] :- H2T msg to send post-reset complete done
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* BIT [31 : 3] :- reserved
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*/
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A_UINT32 h2t_msg;
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struct {
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A_UINT32 pre_reset_done : 1, /* BIT [0] */
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post_reset_start_done : 1, /* BIT [1] */
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post_reset_complete_done : 1, /* BIT [2] */
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rsvd_h2t : 29; /* BIT [31 : 3] */
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};
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};
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} POSTPACK htt_umac_hang_recovery_msg_shmem_t;
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_BYTES \
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(sizeof(htt_umac_hang_recovery_msg_shmem_t))
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DWORDS \
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(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_BYTES >> 2)
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/* dword1 - b'0 - do_pre_reset */
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_M 0x00000001
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_S 0
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_GET(word1) \
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(((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_M) >> \
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HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_S)
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_SET(word1, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET, _val); \
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((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_PRE_RESET_S));\
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} while (0)
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/* dword1 - b'1 - do_post_reset_start */
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_M 0x00000002
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_S 1
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_GET(word1) \
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(((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_M) >> \
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HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_S)
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_SET(word1, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START, _val); \
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((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_START_S));\
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} while (0)
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/* dword1 - b'2 - do_post_reset_complete */
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_M 0x00000004
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_S 2
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_GET(word1) \
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(((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_M) >> \
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HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_S)
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_SET(word1, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE, _val); \
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((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_DO_POST_RESET_COMPLETE_S));\
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} while (0)
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/* dword2 - b'0 - pre_reset_done */
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_M 0x00000001
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S 0
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_GET(word2) \
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(((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_M) >> \
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HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S)
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_SET(word2, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE, _val); \
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((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S));\
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} while (0)
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/* dword2 - b'1 - post_reset_start_done */
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_M 0x00000002
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_S 1
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_GET(word2) \
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(((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_M) >> \
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HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_S)
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_SET(word2, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE, _val); \
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((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_START_DONE_S));\
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} while (0)
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/* dword2 - b'2 - post_reset_complete_done */
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_M 0x00000004
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_S 2
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_GET(word2) \
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(((word2) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_M) >> \
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HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_S)
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#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_SET(word2, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE, _val); \
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((word2) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_POST_RESET_COMPLETE_DONE_S));\
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} while (0)
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/**
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* @brief HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP message
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*
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* @details
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* The HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP message is sent
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* by the host to provide prerequisite info to target for the UMAC hang
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* recovery feature.
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* The info sent in this H2T message are T2H message method, H2T message
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* method, T2H MSI interrupt number and physical start address, size of
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* the shared memory (refers to the shared memory dedicated for messaging
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* between host and target when the DUT is in UMAC hang recovery mode).
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* This H2T message is expected to be only sent if the WMI service bit
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* WMI_SERVICE_UMAC_HANG_RECOVERY_SUPPORT was firstly indicated by the target.
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*
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* |31 16|15 12|11 8|7 0|
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* |-------------------------------+--------------+--------------+------------|
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* | reserved |h2t msg method|t2h msg method| msg_type |
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* |--------------------------------------------------------------------------|
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||||
* | t2h msi interrupt number |
|
||||
* |--------------------------------------------------------------------------|
|
||||
* | shared memory area size |
|
||||
* |--------------------------------------------------------------------------|
|
||||
* | shared memory area physical address low |
|
||||
* |--------------------------------------------------------------------------|
|
||||
* | shared memory area physical address high |
|
||||
* |--------------------------------------------------------------------------|
|
||||
*
|
||||
* The message is interpreted as follows:
|
||||
* dword0 - b'0:7 - msg_type (= HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SETUP)
|
||||
* b'8:11 - t2h_msg_method: indicates method to be used for
|
||||
* T2H communication in UMAC hang recovery mode.
|
||||
* Value zero indicates MSI interrupt (default method).
|
||||
* Refer to htt_umac_hang_recovery_msg_method enum.
|
||||
* b'12:15 - h2t_msg_method: indicates method to be used for
|
||||
* H2T communication in UMAC hang recovery mode.
|
||||
* Value zero indicates polling by target for this h2t msg
|
||||
* during UMAC hang recovery mode.
|
||||
* Refer to htt_umac_hang_recovery_msg_method enum.
|
||||
* b'16:31 - reserved.
|
||||
* dword1 - b'0:31 - t2h_msi_data: MSI data to be used for
|
||||
* T2H communication in UMAC hang recovery mode.
|
||||
* dword2 - b'0:31 - size: size of shared memory dedicated for messaging
|
||||
* only when in UMAC hang recovery mode.
|
||||
* This refers to size in bytes.
|
||||
* dword3 - b'0:31 - physical_address_lo: lower 32 bit physical address
|
||||
* of the shared memory dedicated for messaging only when
|
||||
* in UMAC hang recovery mode.
|
||||
* dword4 - b'0:31 - physical_address_hi: higher 32 bit physical address
|
||||
* of the shared memory dedicated for messaging only when
|
||||
* in UMAC hang recovery mode.
|
||||
*/
|
||||
|
||||
/* t2h_msg_method and h2t_msg_method */
|
||||
enum htt_umac_hang_recovery_msg_method {
|
||||
htt_umac_hang_recovery_msg_t2h_msi_and_h2t_polling = 0,
|
||||
};
|
||||
|
||||
PREPACK typedef struct {
|
||||
A_UINT32 msg_type : 8,
|
||||
t2h_msg_method : 4,
|
||||
h2t_msg_method : 4,
|
||||
reserved : 16;
|
||||
A_UINT32 t2h_msi_data;
|
||||
/* size bytes and physical address of shared memory. */
|
||||
struct htt_h2t_host_paddr_size_entry_t msg_shared_mem;
|
||||
} POSTPACK htt_h2t_umac_hang_recovery_prerequisite_setup_t;
|
||||
|
||||
#define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_BYTES \
|
||||
(sizeof(htt_h2t_umac_hang_recovery_prerequisite_setup_t))
|
||||
#define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_DWORDS \
|
||||
(HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_BYTES >> 2)
|
||||
|
||||
#define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_M 0x00000F00
|
||||
#define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_S 8
|
||||
#define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_GET(word0) \
|
||||
(((word0) & HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_M) >> \
|
||||
HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_S)
|
||||
#define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_SET(word0, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD, _val); \
|
||||
((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_T2H_MSG_METHOD_S));\
|
||||
} while (0)
|
||||
|
||||
#define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_M 0x0000F000
|
||||
#define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_S 12
|
||||
#define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_GET(word0) \
|
||||
(((word0) & HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_M) >> \
|
||||
HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_S)
|
||||
#define HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_SET(word0, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD, _val); \
|
||||
((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP_H2T_MSG_METHOD_S));\
|
||||
} while (0)
|
||||
|
||||
|
||||
/*=== target -> host messages ===============================================*/
|
||||
|
|
@ -9661,6 +9912,9 @@ enum htt_t2h_msg_type {
|
|||
HTT_T2H_MSG_TYPE_SAWF_MSDUQ_INFO_IND = 0x2e,
|
||||
HTT_T2H_SAWF_MSDUQ_INFO_IND = 0x2e, /* alias */
|
||||
HTT_T2H_MSG_TYPE_STREAMING_STATS_IND = 0x2f,
|
||||
HTT_T2H_PPDU_ID_FMT_IND = 0x30,
|
||||
HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN = 0x31,
|
||||
HTT_T2H_MSG_TYPE_RX_DELBA_EXTN = 0x32,
|
||||
|
||||
|
||||
HTT_T2H_MSG_TYPE_TEST,
|
||||
|
|
@ -13158,6 +13412,156 @@ typedef enum {
|
|||
|
||||
#define HTT_RX_DELBA_BYTES 4
|
||||
|
||||
|
||||
/**
|
||||
* @brief target -> host rx ADDBA / DELBA message definitions
|
||||
*
|
||||
* MSG_TYPE => HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN
|
||||
*
|
||||
* @details
|
||||
* The following diagram shows the format of the rx ADDBA extn message sent
|
||||
* from the target to the host:
|
||||
*
|
||||
* |31 20|19 16|15 13|12 8|7 0|
|
||||
* |---------------------------------------------------------------------|
|
||||
* | peer ID | TID | reserved | msg type |
|
||||
* |---------------------------------------------------------------------|
|
||||
* | reserved | window size |
|
||||
* |---------------------------------------------------------------------|
|
||||
*
|
||||
* MSG_TYPE => HTT_T2H_MSG_TYPE_RX_DELBA_EXTN
|
||||
*
|
||||
* The following diagram shows the format of the rx DELBA message sent
|
||||
* from the target to the host:
|
||||
*
|
||||
* |31 20|19 16|15 13|12 10|9 8|7 0|
|
||||
* |---------------------------------------------------------------------|
|
||||
* | peer ID | TID | reserved | IR| msg type |
|
||||
* |---------------------------------------------------------------------|
|
||||
* | reserved | window size |
|
||||
* |---------------------------------------------------------------------|
|
||||
*
|
||||
* The following field definitions describe the format of the rx ADDBA
|
||||
* and DELBA messages sent from the target to the host.
|
||||
* - MSG_TYPE
|
||||
* Bits 7:0
|
||||
* Purpose: identifies this as an rx ADDBA or DELBA message
|
||||
* Value: ADDBA -> 0x31 (HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN),
|
||||
* DELBA -> 0x32 (HTT_T2H_MSG_TYPE_RX_DELBA_EXTN)
|
||||
* - IR (initiator / recipient)
|
||||
* Bits 9:8 (DELBA only)
|
||||
* Purpose: specify whether the DELBA handshake was initiated by the
|
||||
* local STA/AP, or by the peer STA/AP
|
||||
* Value:
|
||||
* 0 - unspecified
|
||||
* 1 - initiator (a.k.a. originator)
|
||||
* 2 - recipient (a.k.a. responder)
|
||||
* 3 - unused / reserved
|
||||
* Value:
|
||||
* block ack window length specified by the received ADDBA/DELBA
|
||||
* management message.
|
||||
* - TID
|
||||
* Bits 19:16
|
||||
* Purpose: Specifies which traffic identifier the ADDBA / DELBA is for.
|
||||
* Value:
|
||||
* TID specified by the received ADDBA or DELBA management message.
|
||||
* - PEER_ID
|
||||
* Bits 31:20
|
||||
* Purpose: Identifies which peer sent the ADDBA / DELBA.
|
||||
* Value:
|
||||
* ID (hash value) used by the host for fast, direct lookup of
|
||||
* host SW peer info, including rx reorder states.
|
||||
* == DWORD 1
|
||||
* - WIN_SIZE
|
||||
* Bits 12:0 for ADDBA, bits 12:0 for DELBA
|
||||
* Purpose: Specifies the length of the block ack window (max = 8191).
|
||||
*/
|
||||
|
||||
#define HTT_RX_ADDBA_EXTN_TID_M 0xf0000
|
||||
#define HTT_RX_ADDBA_EXTN_TID_S 16
|
||||
#define HTT_RX_ADDBA_EXTN_PEER_ID_M 0xfff00000
|
||||
#define HTT_RX_ADDBA_EXTN_PEER_ID_S 20
|
||||
|
||||
/*--- Dword 0 ---*/
|
||||
#define HTT_RX_ADDBA_EXTN_TID_SET(word, value) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_ADDBA_EXTN_TID, value); \
|
||||
(word) |= (value) << HTT_RX_ADDBA_EXTN_TID_S; \
|
||||
} while (0)
|
||||
#define HTT_RX_ADDBA_EXTN_TID_GET(word) \
|
||||
(((word) & HTT_RX_ADDBA_EXTN_TID_M) >> HTT_RX_ADDBA_EXTN_TID_S)
|
||||
|
||||
#define HTT_RX_ADDBA_EXTN_PEER_ID_SET(word, value) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_ADDBA_EXTN_PEER_ID, value); \
|
||||
(word) |= (value) << HTT_RX_ADDBA_EXTN_PEER_ID_S; \
|
||||
} while (0)
|
||||
#define HTT_RX_ADDBA_EXTN_PEER_ID_GET(word) \
|
||||
(((word) & HTT_RX_ADDBA_EXTN_PEER_ID_M) >> HTT_RX_ADDBA_EXTN_PEER_ID_S)
|
||||
|
||||
/*--- Dword 1 ---*/
|
||||
#define HTT_RX_ADDBA_EXTN_WIN_SIZE_M 0x1fff
|
||||
#define HTT_RX_ADDBA_EXTN_WIN_SIZE_S 0
|
||||
|
||||
#define HTT_RX_ADDBA_EXTN_WIN_SIZE_SET(word, value) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_ADDBA_EXTN_WIN_SIZE, value); \
|
||||
(word) |= (value) << HTT_RX_ADDBA_EXTN_WIN_SIZE_S; \
|
||||
} while (0)
|
||||
|
||||
#define HTT_RX_ADDBA_EXTN_WIN_SIZE_GET(word) \
|
||||
(((word) & HTT_RX_ADDBA_WIN_SIZE_M) >> HTT_RX_ADDBA_WIN_SIZE_S)
|
||||
|
||||
#define HTT_RX_ADDBA_EXTN_BYTES 8
|
||||
|
||||
|
||||
#define HTT_RX_DELBA_EXTN_INITIATOR_M 0x00000300
|
||||
#define HTT_RX_DELBA_EXTN_INITIATOR_S 8
|
||||
#define HTT_RX_DELBA_EXTN_TID_M 0xf0000
|
||||
#define HTT_RX_DELBA_EXTN_TID_S 16
|
||||
#define HTT_RX_DELBA_EXTN_PEER_ID_M 0xfff00000
|
||||
#define HTT_RX_DELBA_EXTN_PEER_ID_S 20
|
||||
|
||||
/*--- Dword 0 ---*/
|
||||
#define HTT_RX_DELBA_INITIATOR_SET(word, value) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_DELBA_INITIATOR, value); \
|
||||
(word) |= (value) << HTT_RX_DELBA_INITIATOR_S; \
|
||||
} while (0)
|
||||
#define HTT_RX_DELBA_INITIATOR_GET(word) \
|
||||
(((word) & HTT_RX_DELBA_INITIATOR_M) >> HTT_RX_DELBA_INITIATOR_S)
|
||||
|
||||
#define HTT_RX_DELBA_EXTN_TID_SET(word, value) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_DELBA_EXTN_TID, value); \
|
||||
(word) |= (value) << HTT_RX_DELBA_EXTN_TID_S; \
|
||||
} while (0)
|
||||
#define HTT_RX_DELBA_EXTN_TID_GET(word) \
|
||||
(((word) & HTT_RX_DELBA_EXTN_TID_M) >> HTT_RX_DELBA_EXTN_TID_S)
|
||||
|
||||
#define HTT_RX_DELBA_EXTN_PEER_ID_SET(word, value) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_DELBA_EXTN_PEER_ID, value); \
|
||||
(word) |= (value) << HTT_RX_DELBA_EXTN_PEER_ID_S; \
|
||||
} while (0)
|
||||
#define HTT_RX_DELBA_EXTN_PEER_ID_GET(word) \
|
||||
(((word) & HTT_RX_DELBA_EXTN_PEER_ID_M) >> HTT_RX_DELBA_EXTN_PEER_ID_S)
|
||||
|
||||
/*--- Dword 1 ---*/
|
||||
#define HTT_RX_DELBA_EXTN_WIN_SIZE_M 0x1fff
|
||||
#define HTT_RX_DELBA_EXTN_WIN_SIZE_S 0
|
||||
|
||||
#define HTT_RX_DELBA_EXTN_WIN_SIZE_SET(word, value) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_DELBA_EXTN_WIN_SIZE, value); \
|
||||
(word) |= (value) << HTT_RX_DELBA_EXTN_WIN_SIZE_S; \
|
||||
} while (0)
|
||||
#define HTT_RX_DELBA_EXTN_WIN_SIZE_GET(word) \
|
||||
(((word) & HTT_RX_DELBA_EXTN_WIN_SIZE_M) >> HTT_RX_DELBA_EXTN_WIN_SIZE_S)
|
||||
|
||||
#define HTT_RX_DELBA_EXTN_BYTES 8
|
||||
|
||||
|
||||
/**
|
||||
* @brief tx queue group information element definition
|
||||
*
|
||||
|
|
@ -18412,4 +18816,282 @@ PREPACK struct htt_t2h_sawf_msduq_event {
|
|||
} while (0)
|
||||
|
||||
|
||||
/**
|
||||
* @brief target -> PPDU id format indication
|
||||
*
|
||||
* MSG_TYPE => HTT_T2H_PPDU_ID_FMT_IND
|
||||
*
|
||||
* @details
|
||||
* The following field definitions describe the format of the HTT target
|
||||
* to host PPDU ID format indication message.
|
||||
* hwsch_cmd_id :- A number per ring, increases by one with each HWSCH command.
|
||||
* ring_id :- HWSCH ring id in which this PPDU was enqueued.
|
||||
* seq_idx :- Sequence control index of this PPDU.
|
||||
* link_id :- HW link ID of the link in which the PPDU was enqueued.
|
||||
* seq_cmd_type:- WHAL_TXSEND_FTYPE (SU Data, MU Data, SGEN frames etc.)
|
||||
* tqm_cmd:-
|
||||
*
|
||||
* |31 27|26 22|21 17| 16 |15 11|10 8|7 6|5 1| 0 |
|
||||
* |--------------------------------------------------+------------------------|
|
||||
* | rsvd0 | msg type |
|
||||
* |-----+----------+----------+---------+-----+----------+----------+---------|
|
||||
* |rsvd2|ring_id OF|ring_id NB|ring_id V|rsvd1|cmd_id OF |cmd_id NB |cmd_id V |
|
||||
* |-----+----------+----------+---------+-----+----------+----------+---------|
|
||||
* |rsvd4|link_id OF|link_id NB|link_id V|rsvd3|seq_idx OF|seq_idx NB|seq_idx V|
|
||||
* |-----+----------+----------+---------+-----+----------+----------+---------|
|
||||
* |rsvd6|tqm_cmd OF|tqm_cmd NB|tqm_cmd V|rsvd5|seq_cmd OF|seq_cmd NB|seq_cmd V|
|
||||
* |-----+----------+----------+---------+-----+----------+----------+---------|
|
||||
* |rsvd8| crc OF | crc NB | crc V |rsvd7|mac_id OF |mac_id NB |mac_id V |
|
||||
* |-----+----------+----------+---------+-----+----------+----------+---------|
|
||||
* Where: OF = bit offset, NB = number of bits, V = valid
|
||||
* The message is interpreted as follows:
|
||||
*
|
||||
* dword0 - b'7:0 - msg_type: This will be set to
|
||||
* HTT_T2H_PPDU_ID_FMT_IND
|
||||
* value: 0x30
|
||||
*
|
||||
* dword0 - b'31:8 - reserved
|
||||
*
|
||||
* dword1 - b'0:0 - field to indicate whether hwsch_cmd_id is valid or not
|
||||
*
|
||||
* dword1 - b'5:1 - number of bits in hwsch_cmd_id
|
||||
*
|
||||
* dword1 - b'10:6 - offset of hwsch_cmd_id (in number of bits)
|
||||
*
|
||||
* dword1 - b'15:11 - reserved for future use
|
||||
*
|
||||
* dword1 - b'16:16 - field to indicate whether ring_id is valid or not
|
||||
*
|
||||
* dword1 - b'21:17 - number of bits in ring_id
|
||||
*
|
||||
* dword1 - b'26:22 - offset of ring_id (in number of bits)
|
||||
*
|
||||
* dword1 - b'31:27 - reserved for future use
|
||||
*
|
||||
* dword2 - b'0:0 - field to indicate whether sequence index is valid or not
|
||||
*
|
||||
* dword2 - b'5:1 - number of bits in sequence index
|
||||
*
|
||||
* dword2 - b'10:6 - offset of sequence index (in number of bits)
|
||||
*
|
||||
* dword2 - b'15:11 - reserved for future use
|
||||
*
|
||||
* dword2 - b'16:16 - field to indicate whether link_id is valid or not
|
||||
*
|
||||
* dword2 - b'21:17 - number of bits in link_id
|
||||
*
|
||||
* dword2 - b'26:22 - offset of link_id (in number of bits)
|
||||
*
|
||||
* dword2 - b'31:27 - reserved for future use
|
||||
*
|
||||
* dword3 - b'0:0 - field to indicate whether seq_cmd_type is valid or not
|
||||
*
|
||||
* dword3 - b'5:1 - number of bits in seq_cmd_type
|
||||
*
|
||||
* dword3 - b'10:6 - offset of seq_cmd_type (in number of bits)
|
||||
*
|
||||
* dword3 - b'15:11 - reserved for future use
|
||||
*
|
||||
* dword3 - b'16:16 - field to indicate whether tqm_cmd is valid or not
|
||||
*
|
||||
* dword3 - b'21:17 - number of bits in tqm_cmd
|
||||
*
|
||||
* dword3 - b'26:22 - offset of tqm_cmd (in number of bits)
|
||||
*
|
||||
* dword3 - b'31:27 - reserved for future use
|
||||
*
|
||||
* dword4 - b'0:0 - field to indicate whether mac_id is valid or not
|
||||
*
|
||||
* dword4 - b'5:1 - number of bits in mac_id
|
||||
*
|
||||
* dword4 - b'10:6 - offset of mac_id (in number of bits)
|
||||
*
|
||||
* dword4 - b'15:11 - reserved for future use
|
||||
*
|
||||
* dword4 - b'16:16 - field to indicate whether crc is valid or not
|
||||
*
|
||||
* dword4 - b'21:17 - number of bits in crc
|
||||
*
|
||||
* dword4 - b'26:22 - offset of crc (in number of bits)
|
||||
*
|
||||
* dword4 - b'31:27 - reserved for future use
|
||||
*
|
||||
*/
|
||||
|
||||
#define HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_M 0x00000001
|
||||
#define HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_S 0
|
||||
|
||||
#define HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_M 0x0000003E
|
||||
#define HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_S 1
|
||||
|
||||
#define HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_M 0x000007C0
|
||||
#define HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_S 6
|
||||
|
||||
#define HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_M 0x00010000
|
||||
#define HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_S 16
|
||||
|
||||
#define HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_M 0x003E0000
|
||||
#define HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_S 17
|
||||
|
||||
#define HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_M 0x07C00000
|
||||
#define HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_S 22
|
||||
|
||||
|
||||
/* macros for accessing lower 16 bits in dword */
|
||||
#define HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0(word, value) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_VALID_BITS15_0, value); \
|
||||
(word) |= (value) << HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_S; \
|
||||
} while (0)
|
||||
#define HTT_PPDU_ID_FMT_IND_VALID_GET_BITS15_0(word) \
|
||||
(((word) & HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_M) >> HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_S)
|
||||
|
||||
#define HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0(word, value) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_BITS_BITS15_0, value); \
|
||||
(word) |= (value) << HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_S; \
|
||||
} while (0)
|
||||
#define HTT_PPDU_ID_FMT_IND_BITS_GET_BITS15_0(word) \
|
||||
(((word) & HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_M) >> HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_S)
|
||||
|
||||
#define HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0(word, value) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0, value); \
|
||||
(word) |= (value) << HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_S; \
|
||||
} while (0)
|
||||
#define HTT_PPDU_ID_FMT_IND_OFFSET_GET_BITS15_0(word) \
|
||||
(((word) & HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_M) >> HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_S)
|
||||
|
||||
/* macros for accessing upper 16 bits in dword */
|
||||
#define HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16(word, value) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_VALID_BITS31_16, value); \
|
||||
(word) |= (value) << HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_S; \
|
||||
} while (0)
|
||||
#define HTT_PPDU_ID_FMT_IND_VALID_GET_BITS31_16(word) \
|
||||
(((word) & HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_M) >> HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_S)
|
||||
|
||||
#define HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16(word, value) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_BITS_BITS31_16, value); \
|
||||
(word) |= (value) << HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_S; \
|
||||
} while (0)
|
||||
#define HTT_PPDU_ID_FMT_IND_BITS_GET_BITS31_16(word) \
|
||||
(((word) & HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_M) >> HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_S)
|
||||
|
||||
#define HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16(word, value) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16, value); \
|
||||
(word) |= (value) << HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_S; \
|
||||
} while (0)
|
||||
#define HTT_PPDU_ID_FMT_IND_OFFSET_GET_BITS31_16(word) \
|
||||
(((word) & HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_M) >> HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_S)
|
||||
|
||||
|
||||
#define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_VALID_SET \
|
||||
HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0
|
||||
#define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_BITS_SET \
|
||||
HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0
|
||||
#define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_OFFSET_SET \
|
||||
HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0
|
||||
|
||||
#define HTT_PPDU_ID_FMT_IND_RING_ID_VALID_SET \
|
||||
HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16
|
||||
#define HTT_PPDU_ID_FMT_IND_RING_ID_BITS_SET \
|
||||
HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16
|
||||
#define HTT_PPDU_ID_FMT_IND_RING_ID_OFFSET_SET \
|
||||
HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16
|
||||
|
||||
#define HTT_PPDU_ID_FMT_IND_SEQ_IDX_VALID_SET \
|
||||
HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0
|
||||
#define HTT_PPDU_ID_FMT_IND_SEQ_IDX_BITS_SET \
|
||||
HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0
|
||||
#define HTT_PPDU_ID_FMT_IND_SEQ_IDX_OFFSET_SET \
|
||||
HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0
|
||||
|
||||
#define HTT_PPDU_ID_FMT_IND_LINK_ID_VALID_SET \
|
||||
HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16
|
||||
#define HTT_PPDU_ID_FMT_IND_LINK_ID_BITS_SET \
|
||||
HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16
|
||||
#define HTT_PPDU_ID_FMT_IND_LINK_ID_OFFSET_SET \
|
||||
HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16
|
||||
|
||||
#define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_VALID_SET \
|
||||
HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0
|
||||
#define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_BITS_SET \
|
||||
HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0
|
||||
#define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_OFFSET_SET \
|
||||
HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0
|
||||
|
||||
#define HTT_PPDU_ID_FMT_IND_TQM_CMD_VALID_SET \
|
||||
HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16
|
||||
#define HTT_PPDU_ID_FMT_IND_TQM_CMD_BITS_SET \
|
||||
HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16
|
||||
#define HTT_PPDU_ID_FMT_IND_TQM_CMD_OFFSET_SET \
|
||||
HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16
|
||||
|
||||
#define HTT_PPDU_ID_FMT_IND_MAC_ID_TYPE_VALID_SET \
|
||||
HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0
|
||||
#define HTT_PPDU_ID_FMT_IND_MAC_ID_TYPE_BITS_SET \
|
||||
HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0
|
||||
#define HTT_PPDU_ID_FMT_IND_MAC_ID_TYPE_OFFSET_SET \
|
||||
HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0
|
||||
|
||||
#define HTT_PPDU_ID_FMT_IND_CRC_VALID_SET \
|
||||
HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16
|
||||
#define HTT_PPDU_ID_FMT_IND_CRC_BITS_SET \
|
||||
HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16
|
||||
#define HTT_PPDU_ID_FMT_IND_CRC_OFFSET_SET \
|
||||
HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16
|
||||
|
||||
|
||||
/* offsets in number dwords */
|
||||
#define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_OFFSET 1
|
||||
#define HTT_PPDU_ID_FMT_IND_RING_ID_OFFSET 1
|
||||
#define HTT_PPDU_ID_FMT_IND_SEQ_IDX_OFFSET 2
|
||||
#define HTT_PPDU_ID_FMT_IND_LINK_ID_OFFSET 2
|
||||
#define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_OFFSET 3
|
||||
#define HTT_PPDU_ID_FMT_IND_TQM_CMD_OFFSET 3
|
||||
#define HTT_PPDU_ID_FMT_IND_MAC_ID_OFFSET 4
|
||||
#define HTT_PPDU_ID_FMT_IND_CRC_OFFSET 4
|
||||
|
||||
|
||||
typedef struct {
|
||||
A_UINT32 msg_type: 8, /* bits 7:0 */
|
||||
rsvd0: 24;/* bits 31:8 */
|
||||
A_UINT32 hwsch_cmd_id_valid: 1, /* bits 0:0 */
|
||||
hwsch_cmd_id_bits: 5, /* bits 5:1 */
|
||||
hwsch_cmd_id_offset: 5, /* bits 10:6 */
|
||||
rsvd1: 5, /* bits 15:11 */
|
||||
ring_id_valid: 1, /* bits 16:16 */
|
||||
ring_id_bits: 5, /* bits 21:17 */
|
||||
ring_id_offset: 5, /* bits 26:22 */
|
||||
rsvd2: 5; /* bits 31:27 */
|
||||
A_UINT32 seq_idx_valid: 1, /* bits 0:0 */
|
||||
seq_idx_bits: 5, /* bits 5:1 */
|
||||
seq_idx_offset: 5, /* bits 10:6 */
|
||||
rsvd3: 5, /* bits 15:11 */
|
||||
link_id_valid: 1, /* bits 16:16 */
|
||||
link_id_bits: 5, /* bits 21:17 */
|
||||
link_id_offset: 5, /* bits 26:22 */
|
||||
rsvd4: 5; /* bits 31:27 */
|
||||
A_UINT32 seq_cmd_type_valid: 1, /* bits 0:0 */
|
||||
seq_cmd_type_bits: 5, /* bits 5:1 */
|
||||
seq_cmd_type_offset: 5, /* bits 10:6 */
|
||||
rsvd5: 5, /* bits 15:11 */
|
||||
tqm_cmd_valid: 1, /* bits 16:16 */
|
||||
tqm_cmd_bits: 5, /* bits 21:17 */
|
||||
tqm_cmd_offset: 5, /* bits 26:12 */
|
||||
rsvd6: 5; /* bits 31:27 */
|
||||
A_UINT32 mac_id_valid: 1, /* bits 0:0 */
|
||||
mac_id_bits: 5, /* bits 5:1 */
|
||||
mac_id_offset: 5, /* bits 10:6 */
|
||||
rsvd8: 5, /* bits 15:11 */
|
||||
crc_valid: 1, /* bits 16:16 */
|
||||
crc_bits: 5, /* bits 21:17 */
|
||||
crc_offset: 5, /* bits 26:12 */
|
||||
rsvd9: 5; /* bits 31:27 */
|
||||
} htt_t2h_ppdu_id_fmt_ind_t;
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2021 The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
|
|
@ -53,6 +54,8 @@ enum htt_ppdu_stats_tlv_tag {
|
|||
HTT_PPDU_STATS_USR_COMPLTN_BA_BITMAP_1024_TLV,/* htt_ppdu_stats_user_compltn_ba_bitmap_1024_tlv */
|
||||
HTT_PPDU_STATS_RX_MGMTCTRL_PAYLOAD_TLV, /* htt_ppdu_stats_rx_mgmtctrl_payload_tlv */
|
||||
HTT_PPDU_STATS_FOR_SMU_TLV, /* htt_ppdu_stats_for_smu_tlv */
|
||||
HTT_PPDU_STATS_MLO_TX_RESP_TLV, /* htt_ppdu_stats_mlo_tx_resp_tlv */
|
||||
HTT_PPDU_STATS_MLO_TX_NOTIFICATION_TLV, /* htt_ppdu_stats_mlo_tx_notification_tlv */
|
||||
|
||||
/* New TLV's are added above to this line */
|
||||
HTT_PPDU_STATS_MAX_TAG,
|
||||
|
|
@ -2844,4 +2847,117 @@ typedef struct {
|
|||
A_UINT32 ba_bitmap[1];
|
||||
} htt_ppdu_stats_for_smu_tlv;
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
/*
|
||||
* BIT [ 2 : 0] :- response_reason
|
||||
* BIT [ 6 : 3] :- mlo_change_t1_cts2self
|
||||
* BIT [ 10 : 7] :- mlo_change_t1_ppdu
|
||||
* BIT [ 14 : 11] :- mlo_change_t2_response
|
||||
* BIT [ 18 : 15] :- mlo_change_t3_r2r
|
||||
* BIT [ 19 : 19] :- partner_link_info_valid
|
||||
* BIT [ 22 : 20] :- partner_link_id
|
||||
* BIT [ 27 : 23] :- partner_link_cmd_ring_id
|
||||
* BIT [ 28 : 28] :- dot11ax_trigger_frame_embedded
|
||||
* BIT [ 31 : 29] :- reserved_0a
|
||||
*/
|
||||
A_UINT32 response_reason : 3,
|
||||
mlo_change_t1_cts2self : 4,
|
||||
mlo_change_t1_ppdu : 4,
|
||||
mlo_change_t2_response : 4,
|
||||
mlo_change_t3_r2r : 4,
|
||||
partner_link_info_valid : 1,
|
||||
partner_link_id : 3,
|
||||
partner_link_cmd_ring_id : 5,
|
||||
dot11ax_trigger_frame_embedded : 1,
|
||||
reserved_0a : 3;
|
||||
/*
|
||||
* BIT [ 15 : 0] :- partner_link_schedule_id
|
||||
* BIT [ 31 : 16] :- tx_rx_overlap_duration (microsecond units)
|
||||
*/
|
||||
A_UINT32 partner_link_schedule_id : 16,
|
||||
tx_rx_overlap_duration_us : 16;
|
||||
/*
|
||||
* BIT [ 15 : 0] :- cts2self_duration (microsecond units)
|
||||
* BIT [ 31 : 16] :- ppdu_duration (microsecond units)
|
||||
*/
|
||||
A_UINT32 cts2self_duration_us : 16,
|
||||
ppdu_duration_us : 16;
|
||||
/*
|
||||
* BIT [ 15 : 0] :- response_duration (microsecond units)
|
||||
* BIT [ 31 : 16] :- response_to_response_duration (microsecond units)
|
||||
*/
|
||||
A_UINT32 response_duration_us : 16,
|
||||
response_to_response_duration_us : 16;
|
||||
/*
|
||||
* BIT [ 15 : 0] :- self_link_schedule_id
|
||||
* BIT [ 31 : 16] :- hls_branch_debug_code
|
||||
*/
|
||||
A_UINT32 self_link_schedule_id : 16,
|
||||
hls_branch_debug_code : 16;
|
||||
/*
|
||||
* BIT [ 31 : 0] :- hls_decision_debug_info
|
||||
*/
|
||||
A_UINT32 hls_decision_debug_info : 32;
|
||||
} htt_ppdu_stats_mlo_tx_resp_tlv;
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
/*
|
||||
* BIT [ 2 : 0] :- notification_reason
|
||||
* BIT [ 3 : 3] :- ml_decision
|
||||
* BIT [ 4 : 4] :- cts2self_padding
|
||||
* BIT [ 5 : 5] :- initiated_by_truncated_backoff
|
||||
* BIT [ 8 : 6] :- transmit_start_reason
|
||||
* BIT [ 14 : 9] :- num_users
|
||||
* BIT [ 24 : 15] :- nstr_mlo_sta_id
|
||||
* BIT [ 25 : 25] :- block_self_ml_sync
|
||||
* BIT [ 26 : 26] :- block_partner_ml_sync
|
||||
* BIT [ 27 : 27] :- nstr_mlo_sta_id_valid
|
||||
* BIT [ 31 : 28] :- reserved_0a
|
||||
*/
|
||||
A_UINT32 notification_reason : 3,
|
||||
ml_decision : 1,
|
||||
cts2self_padding : 1,
|
||||
initiated_by_truncated_backoff : 1,
|
||||
transmit_start_reason : 3,
|
||||
num_users : 6,
|
||||
nstr_mlo_sta_id : 10,
|
||||
block_self_ml_sync : 1,
|
||||
block_partner_ml_sync : 1,
|
||||
nstr_mlo_sta_id_valid : 1,
|
||||
reserved_0a : 4;
|
||||
/*
|
||||
* BIT [ 15 : 0] :- pdg_ppdu_duration_adjust_value (microsecond units)
|
||||
* BIT [ 31 : 16] :- mlo_ppdu_duration_adjust_value (microsecond units)
|
||||
*/
|
||||
A_UINT32 pdg_ppdu_duration_adjust_value_us : 16,
|
||||
mlo_ppdu_duration_adjust_value_us : 16;
|
||||
/*
|
||||
* BIT [ 15 : 0] :- response_duration (microsecond units)
|
||||
* BIT [ 31 : 16] :- response_to_response_duration (microsecond units)
|
||||
*/
|
||||
A_UINT32 response_duration_us : 16,
|
||||
response_to_response_duration_us : 16;
|
||||
/*
|
||||
* BIT [ 15 : 0] :- schedule_id
|
||||
* BIT [ 20 : 16] :- cmd_ring_id
|
||||
* BIT [ 31 : 21] :- reserved_1a
|
||||
*/
|
||||
A_UINT32 schedule_id : 16,
|
||||
cmd_ring_id : 5,
|
||||
reserved_1a : 11;
|
||||
/*
|
||||
* BIT [ 31 : 0] :- mlo_reference_timestamp (microsecond units)
|
||||
*/
|
||||
A_UINT32 mlo_reference_timestamp_us : 32;
|
||||
/*
|
||||
* BIT [ 15 : 0] :- cts2self_duration (microsecond units)
|
||||
* BIT [ 31 : 16] :- ppdu_duration (microsecond units)
|
||||
*/
|
||||
A_UINT32 cts2self_duration_us : 16,
|
||||
ppdu_duration_us : 16;
|
||||
} htt_ppdu_stats_mlo_tx_notification_tlv;
|
||||
|
||||
|
||||
#endif //__HTT_PPDU_STATS_H__
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -123,7 +123,21 @@ typedef enum {
|
|||
WLAN_MODULE_STA_MLO_PS, /* 0x59 */ /* MLO PS manager */
|
||||
WLAN_MODULE_MLO_SYNC_SEQ_NUM, /* 0x5a */ /* sync seq num after rm MPDU */
|
||||
WLAN_MODULE_PLCMGR, /* 0x5b */ /* Policy Manager */
|
||||
/* OEM module IDs:
|
||||
* Reserve a small series of module IDs for use in OEM WLAN FW that
|
||||
* interacts with WLAN FW SDK.
|
||||
*/
|
||||
WLAN_MODULE_OEM0, /* 0x5c */
|
||||
WLAN_MODULE_OEM1, /* 0x5d */
|
||||
WLAN_MODULE_OEM2, /* 0x5e */
|
||||
WLAN_MODULE_OEM3, /* 0x5f */
|
||||
WLAN_MODULE_OEM4, /* 0x60 */
|
||||
WLAN_MODULE_OEM5, /* 0x61 */
|
||||
WLAN_MODULE_OEM6, /* 0x62 */
|
||||
WLAN_MODULE_OEM7, /* 0x63 */
|
||||
|
||||
WLAN_MODULE_T2LM, /* 0x64 */
|
||||
WLAN_MODULE_HEALTH_MON, /* 0x65 */
|
||||
|
||||
WLAN_MODULE_ID_MAX,
|
||||
WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX,
|
||||
|
|
|
|||
|
|
@ -587,6 +587,13 @@ typedef enum {
|
|||
WMI_SERVICE_HW_TX_POWER_CAPS_SIGNED_SUPPORT = 334, /* Indicates FW supports updating of Tx power capabilities as signed value */
|
||||
WMI_SERVICE_MULTI_CLIENT_LL_SUPPORT = 335, /* FW supports set param cmd combined for multiple params */
|
||||
WMI_SERVICE_AFC_PAYLOAD_CLEAR_SUPPORT = 336, /* FW supports clearing the AFC response payload in proxy mode */
|
||||
WMI_SERVICE_FW_INI_PARSE_SUPPORT = 337, /* FW supports parsing ini configuration file */
|
||||
WMI_SERVICE_TDLS_6GHZ_SUPPORT = 338, /* FW supports 6GHz TDLS both on base channel and offchannel */
|
||||
WMI_SERVICE_LINKSPEED_ROAM_TRIGGER_SUPPORT = 339, /* FW supports linkspeed trigger roam */
|
||||
WMI_SERVICE_UMAC_HANG_RECOVERY_SUPPORT = 340, /* FW supports recovering system from UMAC hang condition */
|
||||
WMI_SERVICE_COAP_OFFLOAD_SUPPORT = 341, /* FW supports CoAP (the Constrained Application Protocol) offload */
|
||||
WMI_SERVICE_TDLS_WIDEBAND_SUPPORT = 342, /* FW supports Wideband TDLS */
|
||||
WMI_SERVICE_FEATURE_SET_EVENT_SUPPORT = 343, /* FW supports sending of supported feature set event during init time */
|
||||
|
||||
WMI_MAX_EXT2_SERVICE
|
||||
|
||||
|
|
|
|||
|
|
@ -1268,6 +1268,31 @@ typedef enum {
|
|||
WMITLV_TAG_STRUC_wmi_tid_to_link_map,
|
||||
WMITLV_TAG_STRUC_wmi_peer_tid_to_link_map_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_peer_assoc_tid_to_link_map,
|
||||
WMITLV_TAG_STRUC_wmi_peer_delete_mlo_params,
|
||||
WMITLV_TAG_STRUC_wmi_roam_enable_vendor_control_cmd_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_roam_get_vendor_control_param_cmd_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_roam_get_vendor_control_param_event_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_request_halphy_ctrl_path_stats_cmd_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_halphy_ctrl_path_stats_event_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_peer_flush_policy_cmd_fixed_param,
|
||||
WMITLV_TAG_STRUC_WMI_WOW_COAP_ADD_PATTERN_CMD_fixed_param,
|
||||
WMITLV_TAG_STRUC_WMI_WOW_COAP_DEL_PATTERN_CMD_fixed_param,
|
||||
WMITLV_TAG_STRUC_WMI_WOW_COAP_ADD_KEEPALIVE_PATTERN_CMD_fixed_param,
|
||||
WMITLV_TAG_STRUC_WMI_WOW_COAP_DEL_KEEPALIVE_PATTERN_CMD_fixed_param,
|
||||
WMITLV_TAG_STRUC_WMI_WOW_COAP_GET_BUF_INFO_CMD_fixed_param,
|
||||
WMITLV_TAG_STRUC_WMI_WOW_COAP_BUF_INFO_EVENT_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_coap_tuple,
|
||||
WMITLV_TAG_STRUC_wmi_iface_powersave_stats,
|
||||
WMITLV_TAG_STRUC_wmi_roam_bss_info_param,
|
||||
WMITLV_TAG_STRUC_wmi_vendor_control_param,
|
||||
WMITLV_TAG_STRUC_wmi_coex_dbam_cmd_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_coex_dbam_complete_event_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_is_my_mgmt_frame,
|
||||
WMITLV_TAG_STRUC_wmi_health_mon_init_done_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_ipa_link_stats_event_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_ipa_link_stats,
|
||||
WMITLV_TAG_STRUC_wmi_ipa_per_mac_stats,
|
||||
WMITLV_TAG_STRUC_wmi_pdev_featureset_cmd_fixed_param,
|
||||
} WMITLV_TAG_ID;
|
||||
|
||||
/*
|
||||
|
|
@ -1762,6 +1787,17 @@ typedef enum {
|
|||
OP(WMI_PMM_SCRATCH_REG_ALLOCATION_CMDID) \
|
||||
OP(WMI_PEER_TX_FILTER_CMDID) \
|
||||
OP(WMI_MLO_PEER_TID_TO_LINK_MAP_CMDID) \
|
||||
OP(WMI_ROAM_ENABLE_VENDOR_CONTROL_CMDID) \
|
||||
OP(WMI_ROAM_GET_VENDOR_CONTROL_PARAM_CMDID) \
|
||||
OP(WMI_REQUEST_HALPHY_CTRL_PATH_STATS_CMDID) \
|
||||
OP(WMI_PEER_FLUSH_POLICY_CMDID) \
|
||||
OP(WMI_WOW_COAP_ADD_PATTERN_CMDID) \
|
||||
OP(WMI_WOW_COAP_DEL_PATTERN_CMDID) \
|
||||
OP(WMI_WOW_COAP_ADD_KEEPALIVE_PATTERN_CMDID) \
|
||||
OP(WMI_WOW_COAP_DEL_KEEPALIVE_PATTERN_CMDID) \
|
||||
OP(WMI_WOW_COAP_GET_BUF_INFO_CMDID) \
|
||||
OP(WMI_COEX_DBAM_CMDID) \
|
||||
OP(WMI_PDEV_FEATURESET_CMDID) \
|
||||
/* add new CMD_LIST elements above this line */
|
||||
|
||||
|
||||
|
|
@ -2048,6 +2084,12 @@ typedef enum {
|
|||
OP(WMI_PMM_AVAILABLE_SCRATCH_REG_EVENTID) \
|
||||
OP(WMI_PMM_SCRATCH_REG_ALLOCATION_COMPLETE_EVENTID) \
|
||||
OP(WMI_VDEV_LATENCY_LEVEL_EVENTID) \
|
||||
OP(WMI_ROAM_GET_VENDOR_CONTROL_PARAM_EVENTID) \
|
||||
OP(WMI_HALPHY_CTRL_PATH_STATS_EVENTID) \
|
||||
OP(WMI_WOW_COAP_BUF_INFO_EVENTID) \
|
||||
OP(WMI_COEX_DBAM_COMPLETE_EVENTID) \
|
||||
OP(WMI_HEALTH_MON_INIT_DONE_EVENTID) \
|
||||
OP(WMI_IPA_LINK_STATS_EVENTID) \
|
||||
/* add new EVT_LIST elements above this line */
|
||||
|
||||
|
||||
|
|
@ -2073,7 +2115,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CREATE_CMDID);
|
|||
|
||||
/* Peer delete Cmd */
|
||||
#define WMITLV_TABLE_WMI_PEER_DELETE_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_delete_cmd_fixed_param, wmi_peer_delete_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_delete_cmd_fixed_param, wmi_peer_delete_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_delete_mlo_params, mlo_params, WMITLV_SIZE_VAR)
|
||||
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_PEER_DELETE_CMDID);
|
||||
|
||||
|
|
@ -4188,9 +4231,15 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_FIPS_EXTEND_CMDID);
|
|||
|
||||
/* FIPS mode set cmd */
|
||||
#define WMITLV_TABLE_WMI_PDEV_FIPS_MODE_SET_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_fips_mode_set_cmd_fixed_param, wmi_pdev_fips_mode_set_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_fips_mode_set_cmd_fixed_param, wmi_pdev_fips_mode_set_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_FIPS_MODE_SET_CMDID);
|
||||
|
||||
/* Featureset cmd */
|
||||
#define WMITLV_TABLE_WMI_PDEV_FEATURESET_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_featureset_cmd_fixed_param, wmi_pdev_featureset_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, feature_set_bitmap, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_FEATURESET_CMDID);
|
||||
|
||||
/* get CCK ANI level */
|
||||
#define WMITLV_TABLE_WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_get_ani_cck_config_cmd_fixed_param, wmi_pdev_get_ani_cck_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
|
|
@ -4397,6 +4446,14 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_PEER_STATS_INFO_CMDID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, odd_addr_read_args, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_CTRL_PATH_STATS_CMDID);
|
||||
|
||||
/* Request Halphy Stats through Ctrl Path */
|
||||
#define WMITLV_TABLE_WMI_REQUEST_HALPHY_CTRL_PATH_STATS_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_request_halphy_ctrl_path_stats_cmd_fixed_param, wmi_request_halphy_ctrl_path_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)\
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, pdev_ids, WMITLV_SIZE_VAR)\
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_ids, WMITLV_SIZE_VAR)\
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, mac_addr_list, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_HALPHY_CTRL_PATH_STATS_CMDID);
|
||||
|
||||
/* Host sets the current country code */
|
||||
#define WMITLV_TABLE_WMI_SET_CURRENT_COUNTRY_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_set_current_country_cmd_fixed_param, wmi_set_current_country_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
|
|
@ -4983,6 +5040,16 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_MU_SNIF_CMDID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_set_param_cmd_fixed_param, wmi_roam_set_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SET_PARAM_CMDID);
|
||||
|
||||
/* Roam enable vendor control Cmd */
|
||||
#define WMITLV_TABLE_WMI_ROAM_ENABLE_VENDOR_CONTROL_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_enable_vendor_control_cmd_fixed_param, wmi_roam_enable_vendor_control_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_ENABLE_VENDOR_CONTROL_CMDID);
|
||||
|
||||
/* Roam Get vendor control Param Cmd */
|
||||
#define WMITLV_TABLE_WMI_ROAM_GET_VENDOR_CONTROL_PARAM_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_get_vendor_control_param_cmd_fixed_param, wmi_roam_get_vendor_control_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_GET_VENDOR_CONTROL_PARAM_CMDID);
|
||||
|
||||
#define WMITLV_TABLE_WMI_SAWF_SVC_CLASS_CFG_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sawf_svc_class_cfg_cmd_fixed_param, wmi_sawf_svc_class_cfg_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_SAWF_SVC_CLASS_CFG_CMDID);
|
||||
|
|
@ -5019,6 +5086,53 @@ WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PASN_DEAUTH_CMD);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pmm_scratch_reg_info, scratch_reg_info, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_PMM_SCRATCH_REG_ALLOCATION_CMDID);
|
||||
|
||||
/* Peer flush Policy Cmd */
|
||||
#define WMITLV_TABLE_WMI_PEER_FLUSH_POLICY_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_flush_policy_cmd_fixed_param, wmi_peer_flush_policy_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_PEER_FLUSH_POLICY_CMDID);
|
||||
|
||||
/** COAP Add Pattern Cmd
|
||||
* TLV (tag length value ) parameters follow the coap_add_pattern
|
||||
* structure. The TLV's are:
|
||||
* A_UINT8 verify_string[];
|
||||
* A_UINT8 coapmsg[];
|
||||
*/
|
||||
#define WMITLV_TABLE_WMI_WOW_COAP_ADD_PATTERN_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_COAP_ADD_PATTERN_CMD_fixed_param, WMI_WOW_COAP_ADD_PATTERN_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, verify_string, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, coapmsg, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_WOW_COAP_ADD_PATTERN_CMDID);
|
||||
|
||||
/* COAP Del Pattern Cmd */
|
||||
#define WMITLV_TABLE_WMI_WOW_COAP_DEL_PATTERN_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_COAP_DEL_PATTERN_CMD_fixed_param, WMI_WOW_COAP_DEL_PATTERN_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_WOW_COAP_DEL_PATTERN_CMDID);
|
||||
|
||||
/** COAP Add Keepalive Pattern Cmd
|
||||
* TLV (tag length value ) parameters follow the coap_add_keepalive_pattern
|
||||
* structure. The TLV's are:
|
||||
* A_UINT8 coapmsg[];
|
||||
*/
|
||||
#define WMITLV_TABLE_WMI_WOW_COAP_ADD_KEEPALIVE_PATTERN_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_COAP_ADD_KEEPALIVE_PATTERN_CMD_fixed_param, WMI_WOW_COAP_ADD_KEEPALIVE_PATTERN_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, coapmsg, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_WOW_COAP_ADD_KEEPALIVE_PATTERN_CMDID);
|
||||
|
||||
/* COAP Del Keepalive Pattern Cmd */
|
||||
#define WMITLV_TABLE_WMI_WOW_COAP_DEL_KEEPALIVE_PATTERN_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_COAP_DEL_KEEPALIVE_PATTERN_CMD_fixed_param, WMI_WOW_COAP_DEL_KEEPALIVE_PATTERN_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_WOW_COAP_DEL_KEEPALIVE_PATTERN_CMDID);
|
||||
|
||||
/* COAP Get Buffer Info Cmd */
|
||||
#define WMITLV_TABLE_WMI_WOW_COAP_GET_BUF_INFO_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_COAP_GET_BUF_INFO_CMD_fixed_param, WMI_WOW_COAP_GET_BUF_INFO_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_WOW_COAP_GET_BUF_INFO_CMDID);
|
||||
|
||||
/* coex dbam cmd */
|
||||
#define WMITLV_TABLE_WMI_COEX_DBAM_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_dbam_cmd_fixed_param, wmi_coex_dbam_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_COEX_DBAM_CMDID);
|
||||
|
||||
|
||||
|
||||
/************************** TLV definitions of WMI events *******************************/
|
||||
|
|
@ -5285,7 +5399,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STA_KICKOUT_EVENTID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mgmt_rx_params_ext, mgmt_rx_params_ext, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_frame_pn_params, pn_params, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mgmt_ml_info, ml_info, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bpcc_bufp, WMITLV_SIZE_VAR)
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bpcc_bufp, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_is_my_mgmt_frame, my_frame, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_RX_EVENTID);
|
||||
|
||||
/* Management Rx FW Consumed Event */
|
||||
|
|
@ -5334,7 +5449,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_AGGR_STATE_TRIG_EVENTID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_event_fixed_param, wmi_roam_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, deauth_disassoc_frame, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_hw_mode_transition_event_fixed_param, hw_mode_transition_fixed_param, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_hw_mode_response_vdev_mac_entry, wmi_pdev_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR)
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_hw_mode_response_vdev_mac_entry, wmi_pdev_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_bss_info_param, bss_info_param, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_EVENTID);
|
||||
|
||||
/* Roam Synch Event */
|
||||
|
|
@ -5370,6 +5486,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SYNCH_FRAME_EVENTID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, frame, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_FRAME_EVENTID);
|
||||
|
||||
/* Get Roam Vendor Control Param Event */
|
||||
#define WMITLV_TABLE_WMI_ROAM_GET_VENDOR_CONTROL_PARAM_EVENTID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_get_vendor_control_param_event_fixed_param, wmi_roam_get_vendor_control_param_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vendor_control_param, vendor_control_param, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_GET_VENDOR_CONTROL_PARAM_EVENTID);
|
||||
|
||||
/* WOW Wakeup Host Event */
|
||||
/* NOTE: Make sure wow_bitmap_info can be zero or one elements only */
|
||||
#define WMITLV_TABLE_WMI_WOW_WAKEUP_HOST_EVENTID(id,op,buf,len) \
|
||||
|
|
@ -5539,7 +5661,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_OEM_DMA_BUF_RELEASE_EVENTID);
|
|||
/* oem data event */
|
||||
#define WMITLV_TABLE_WMI_OEM_DATA_EVENTID(id,op, buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_oem_data_event_fixed_param, wmi_oem_data_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, file_name, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_OEM_DATA_EVENTID);
|
||||
|
||||
/* HOST SWBA Event */
|
||||
|
|
@ -5620,7 +5743,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_iface_link_stats_event_fixed_param, wmi_iface_link_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_link_stats, iface_link_stats, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wmm_ac_stats, ac, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_offload_stats, iface_offload_stats, WMITLV_SIZE_VAR)
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_offload_stats, iface_offload_stats, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_powersave_stats, iface_powersave_stats, WMITLV_SIZE_VAR)
|
||||
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_IFACE_LINK_STATS_EVENTID);
|
||||
|
||||
|
|
@ -5640,6 +5764,14 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_LINK_STATS_EVENTID);
|
|||
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_RADIO_LINK_STATS_EVENTID);
|
||||
|
||||
/* Update ipa stats Event */
|
||||
#define WMITLV_TABLE_WMI_IPA_LINK_STATS_EVENTID(id,op,buf,len)\
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ipa_link_stats_event_fixed_param, wmi_ipa_link_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ipa_link_stats, ipa_stats, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ipa_per_mac_stats, per_mac_stats, WMITLV_SIZE_VAR)
|
||||
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_IPA_LINK_STATS_EVENTID);
|
||||
|
||||
/* Update WLM stats event */
|
||||
#define WMITLV_TABLE_WMI_WLM_STATS_EVENTID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlm_stats_event_fixed_param, wmi_wlm_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
|
|
@ -6429,6 +6561,23 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_afc_stats_struct, ctrl_path_afc_stats, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID);
|
||||
|
||||
/*
|
||||
* Update HALPHY Control Path stats event
|
||||
* Below definition shows TLV packing of HALPHY ctrl path event
|
||||
* Special Patch code is needed on host side to have compatible
|
||||
* HOST Endianness
|
||||
*/
|
||||
#define WMITLV_TABLE_WMI_HALPHY_CTRL_PATH_STATS_EVENTID(id, op, buf, len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_halphy_ctrl_path_stats_event_fixed_param, wmi_halphy_ctrl_path_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tpc_configs, tpc_configs, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_max_reg_power_allowed, regulatory_power, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_INT16, A_INT16, reg_buf, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tpc_rates_array, tpc_rates, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_INT16, A_UINT16, rates_buf, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tpc_ctl_pwr_table, ctl_power, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_INT8, ctl_buf, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_HALPHY_CTRL_PATH_STATS_EVENTID);
|
||||
|
||||
#define WMITLV_TABLE_WMI_RADIO_CHAN_STATS_EVENTID(id, op, buf, len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_radio_chan_stats_event_fixed_param, wmi_radio_chan_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_radio_chan_stats, radio_chan_stats, WMITLV_SIZE_VAR)
|
||||
|
|
@ -6796,6 +6945,23 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PMM_AVAILABLE_SCRATCH_REG_EVENTID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pmm_scratch_reg_allocation_complete_event_fixed_param, wmi_pmm_scratch_reg_allocation_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_PMM_SCRATCH_REG_ALLOCATION_COMPLETE_EVENTID);
|
||||
|
||||
/* COAP buffer info event */
|
||||
#define WMITLV_TABLE_WMI_WOW_COAP_BUF_INFO_EVENTID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_COAP_BUF_INFO_EVENT_fixed_param, WMI_WOW_COAP_BUF_INFO_EVENT_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_coap_tuple, coap_tuple, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, payloads, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_WOW_COAP_BUF_INFO_EVENTID);
|
||||
|
||||
/* coex dbam cmd complete event */
|
||||
#define WMITLV_TABLE_WMI_COEX_DBAM_COMPLETE_EVENTID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_dbam_complete_event_fixed_param, wmi_coex_dbam_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_COEX_DBAM_COMPLETE_EVENTID);
|
||||
|
||||
#define WMITLV_TABLE_WMI_HEALTH_MON_INIT_DONE_EVENTID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_health_mon_init_done_fixed_param, wmi_health_mon_init_done_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_HEALTH_MON_INIT_DONE_EVENTID);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -37,7 +37,7 @@
|
|||
#define __WMI_VER_MINOR_ 0
|
||||
/** WMI revision number has to be incremented when there is a
|
||||
* change that may or may not break compatibility. */
|
||||
#define __WMI_REVISION_ 1148
|
||||
#define __WMI_REVISION_ 1188
|
||||
|
||||
/** The Version Namespace should not be normally changed. Only
|
||||
* host and firmware of the same WMI namespace will work
|
||||
|
|
|
|||
265
drivers/staging/fw-api/hw/kiwi/v1/rx_reo_queue_1k.h
Normal file
265
drivers/staging/fw-api/hw/kiwi/v1/rx_reo_queue_1k.h
Normal file
|
|
@ -0,0 +1,265 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _RX_REO_QUEUE_1K_H_
|
||||
#define _RX_REO_QUEUE_1K_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "uniform_descriptor_header.h"
|
||||
#define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32
|
||||
|
||||
struct rx_reo_queue_1k {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct uniform_descriptor_header descriptor_header;
|
||||
uint32_t rx_bitmap_319_288 : 32;
|
||||
uint32_t rx_bitmap_351_320 : 32;
|
||||
uint32_t rx_bitmap_383_352 : 32;
|
||||
uint32_t rx_bitmap_415_384 : 32;
|
||||
uint32_t rx_bitmap_447_416 : 32;
|
||||
uint32_t rx_bitmap_479_448 : 32;
|
||||
uint32_t rx_bitmap_511_480 : 32;
|
||||
uint32_t rx_bitmap_543_512 : 32;
|
||||
uint32_t rx_bitmap_575_544 : 32;
|
||||
uint32_t rx_bitmap_607_576 : 32;
|
||||
uint32_t rx_bitmap_639_608 : 32;
|
||||
uint32_t rx_bitmap_671_640 : 32;
|
||||
uint32_t rx_bitmap_703_672 : 32;
|
||||
uint32_t rx_bitmap_735_704 : 32;
|
||||
uint32_t rx_bitmap_767_736 : 32;
|
||||
uint32_t rx_bitmap_799_768 : 32;
|
||||
uint32_t rx_bitmap_831_800 : 32;
|
||||
uint32_t rx_bitmap_863_832 : 32;
|
||||
uint32_t rx_bitmap_895_864 : 32;
|
||||
uint32_t rx_bitmap_927_896 : 32;
|
||||
uint32_t rx_bitmap_959_928 : 32;
|
||||
uint32_t rx_bitmap_991_960 : 32;
|
||||
uint32_t rx_bitmap_1023_992 : 32;
|
||||
uint32_t reserved_24 : 32;
|
||||
uint32_t reserved_25 : 32;
|
||||
uint32_t reserved_26 : 32;
|
||||
uint32_t reserved_27 : 32;
|
||||
uint32_t reserved_28 : 32;
|
||||
uint32_t reserved_29 : 32;
|
||||
uint32_t reserved_30 : 32;
|
||||
uint32_t reserved_31 : 32;
|
||||
#else
|
||||
struct uniform_descriptor_header descriptor_header;
|
||||
uint32_t rx_bitmap_319_288 : 32;
|
||||
uint32_t rx_bitmap_351_320 : 32;
|
||||
uint32_t rx_bitmap_383_352 : 32;
|
||||
uint32_t rx_bitmap_415_384 : 32;
|
||||
uint32_t rx_bitmap_447_416 : 32;
|
||||
uint32_t rx_bitmap_479_448 : 32;
|
||||
uint32_t rx_bitmap_511_480 : 32;
|
||||
uint32_t rx_bitmap_543_512 : 32;
|
||||
uint32_t rx_bitmap_575_544 : 32;
|
||||
uint32_t rx_bitmap_607_576 : 32;
|
||||
uint32_t rx_bitmap_639_608 : 32;
|
||||
uint32_t rx_bitmap_671_640 : 32;
|
||||
uint32_t rx_bitmap_703_672 : 32;
|
||||
uint32_t rx_bitmap_735_704 : 32;
|
||||
uint32_t rx_bitmap_767_736 : 32;
|
||||
uint32_t rx_bitmap_799_768 : 32;
|
||||
uint32_t rx_bitmap_831_800 : 32;
|
||||
uint32_t rx_bitmap_863_832 : 32;
|
||||
uint32_t rx_bitmap_895_864 : 32;
|
||||
uint32_t rx_bitmap_927_896 : 32;
|
||||
uint32_t rx_bitmap_959_928 : 32;
|
||||
uint32_t rx_bitmap_991_960 : 32;
|
||||
uint32_t rx_bitmap_1023_992 : 32;
|
||||
uint32_t reserved_24 : 32;
|
||||
uint32_t reserved_25 : 32;
|
||||
uint32_t reserved_26 : 32;
|
||||
uint32_t reserved_27 : 32;
|
||||
uint32_t reserved_28 : 32;
|
||||
uint32_t reserved_29 : 32;
|
||||
uint32_t reserved_30 : 32;
|
||||
uint32_t reserved_31 : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB 0
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB 3
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
|
||||
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
|
||||
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET 0x00000004
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET 0x00000008
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET 0x0000000c
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET 0x00000010
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET 0x00000014
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET 0x00000018
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET 0x0000001c
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET 0x00000020
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET 0x00000024
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET 0x00000028
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET 0x0000002c
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET 0x00000030
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET 0x00000034
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET 0x00000038
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET 0x0000003c
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET 0x00000040
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET 0x00000044
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET 0x00000048
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET 0x0000004c
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET 0x00000050
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET 0x00000054
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET 0x00000058
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET 0x0000005c
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RESERVED_24_OFFSET 0x00000060
|
||||
#define RX_REO_QUEUE_1K_RESERVED_24_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RESERVED_24_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RESERVED_24_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RESERVED_25_OFFSET 0x00000064
|
||||
#define RX_REO_QUEUE_1K_RESERVED_25_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RESERVED_25_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RESERVED_25_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RESERVED_26_OFFSET 0x00000068
|
||||
#define RX_REO_QUEUE_1K_RESERVED_26_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RESERVED_26_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RESERVED_26_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RESERVED_27_OFFSET 0x0000006c
|
||||
#define RX_REO_QUEUE_1K_RESERVED_27_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RESERVED_27_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RESERVED_27_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RESERVED_28_OFFSET 0x00000070
|
||||
#define RX_REO_QUEUE_1K_RESERVED_28_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RESERVED_28_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RESERVED_28_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RESERVED_29_OFFSET 0x00000074
|
||||
#define RX_REO_QUEUE_1K_RESERVED_29_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RESERVED_29_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RESERVED_29_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RESERVED_30_OFFSET 0x00000078
|
||||
#define RX_REO_QUEUE_1K_RESERVED_30_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RESERVED_30_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RESERVED_30_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RESERVED_31_OFFSET 0x0000007c
|
||||
#define RX_REO_QUEUE_1K_RESERVED_31_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RESERVED_31_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RESERVED_31_MASK 0xffffffff
|
||||
|
||||
#endif
|
||||
265
drivers/staging/fw-api/hw/kiwi/v2/rx_reo_queue_1k.h
Normal file
265
drivers/staging/fw-api/hw/kiwi/v2/rx_reo_queue_1k.h
Normal file
|
|
@ -0,0 +1,265 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _RX_REO_QUEUE_1K_H_
|
||||
#define _RX_REO_QUEUE_1K_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "uniform_descriptor_header.h"
|
||||
#define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32
|
||||
|
||||
struct rx_reo_queue_1k {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct uniform_descriptor_header descriptor_header;
|
||||
uint32_t rx_bitmap_319_288 : 32;
|
||||
uint32_t rx_bitmap_351_320 : 32;
|
||||
uint32_t rx_bitmap_383_352 : 32;
|
||||
uint32_t rx_bitmap_415_384 : 32;
|
||||
uint32_t rx_bitmap_447_416 : 32;
|
||||
uint32_t rx_bitmap_479_448 : 32;
|
||||
uint32_t rx_bitmap_511_480 : 32;
|
||||
uint32_t rx_bitmap_543_512 : 32;
|
||||
uint32_t rx_bitmap_575_544 : 32;
|
||||
uint32_t rx_bitmap_607_576 : 32;
|
||||
uint32_t rx_bitmap_639_608 : 32;
|
||||
uint32_t rx_bitmap_671_640 : 32;
|
||||
uint32_t rx_bitmap_703_672 : 32;
|
||||
uint32_t rx_bitmap_735_704 : 32;
|
||||
uint32_t rx_bitmap_767_736 : 32;
|
||||
uint32_t rx_bitmap_799_768 : 32;
|
||||
uint32_t rx_bitmap_831_800 : 32;
|
||||
uint32_t rx_bitmap_863_832 : 32;
|
||||
uint32_t rx_bitmap_895_864 : 32;
|
||||
uint32_t rx_bitmap_927_896 : 32;
|
||||
uint32_t rx_bitmap_959_928 : 32;
|
||||
uint32_t rx_bitmap_991_960 : 32;
|
||||
uint32_t rx_bitmap_1023_992 : 32;
|
||||
uint32_t reserved_24 : 32;
|
||||
uint32_t reserved_25 : 32;
|
||||
uint32_t reserved_26 : 32;
|
||||
uint32_t reserved_27 : 32;
|
||||
uint32_t reserved_28 : 32;
|
||||
uint32_t reserved_29 : 32;
|
||||
uint32_t reserved_30 : 32;
|
||||
uint32_t reserved_31 : 32;
|
||||
#else
|
||||
struct uniform_descriptor_header descriptor_header;
|
||||
uint32_t rx_bitmap_319_288 : 32;
|
||||
uint32_t rx_bitmap_351_320 : 32;
|
||||
uint32_t rx_bitmap_383_352 : 32;
|
||||
uint32_t rx_bitmap_415_384 : 32;
|
||||
uint32_t rx_bitmap_447_416 : 32;
|
||||
uint32_t rx_bitmap_479_448 : 32;
|
||||
uint32_t rx_bitmap_511_480 : 32;
|
||||
uint32_t rx_bitmap_543_512 : 32;
|
||||
uint32_t rx_bitmap_575_544 : 32;
|
||||
uint32_t rx_bitmap_607_576 : 32;
|
||||
uint32_t rx_bitmap_639_608 : 32;
|
||||
uint32_t rx_bitmap_671_640 : 32;
|
||||
uint32_t rx_bitmap_703_672 : 32;
|
||||
uint32_t rx_bitmap_735_704 : 32;
|
||||
uint32_t rx_bitmap_767_736 : 32;
|
||||
uint32_t rx_bitmap_799_768 : 32;
|
||||
uint32_t rx_bitmap_831_800 : 32;
|
||||
uint32_t rx_bitmap_863_832 : 32;
|
||||
uint32_t rx_bitmap_895_864 : 32;
|
||||
uint32_t rx_bitmap_927_896 : 32;
|
||||
uint32_t rx_bitmap_959_928 : 32;
|
||||
uint32_t rx_bitmap_991_960 : 32;
|
||||
uint32_t rx_bitmap_1023_992 : 32;
|
||||
uint32_t reserved_24 : 32;
|
||||
uint32_t reserved_25 : 32;
|
||||
uint32_t reserved_26 : 32;
|
||||
uint32_t reserved_27 : 32;
|
||||
uint32_t reserved_28 : 32;
|
||||
uint32_t reserved_29 : 32;
|
||||
uint32_t reserved_30 : 32;
|
||||
uint32_t reserved_31 : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB 0
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB 3
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
|
||||
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
|
||||
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET 0x00000004
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET 0x00000008
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET 0x0000000c
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET 0x00000010
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET 0x00000014
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET 0x00000018
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET 0x0000001c
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET 0x00000020
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET 0x00000024
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET 0x00000028
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET 0x0000002c
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET 0x00000030
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET 0x00000034
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET 0x00000038
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET 0x0000003c
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET 0x00000040
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET 0x00000044
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET 0x00000048
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET 0x0000004c
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET 0x00000050
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET 0x00000054
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET 0x00000058
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET 0x0000005c
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RESERVED_24_OFFSET 0x00000060
|
||||
#define RX_REO_QUEUE_1K_RESERVED_24_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RESERVED_24_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RESERVED_24_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RESERVED_25_OFFSET 0x00000064
|
||||
#define RX_REO_QUEUE_1K_RESERVED_25_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RESERVED_25_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RESERVED_25_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RESERVED_26_OFFSET 0x00000068
|
||||
#define RX_REO_QUEUE_1K_RESERVED_26_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RESERVED_26_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RESERVED_26_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RESERVED_27_OFFSET 0x0000006c
|
||||
#define RX_REO_QUEUE_1K_RESERVED_27_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RESERVED_27_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RESERVED_27_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RESERVED_28_OFFSET 0x00000070
|
||||
#define RX_REO_QUEUE_1K_RESERVED_28_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RESERVED_28_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RESERVED_28_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RESERVED_29_OFFSET 0x00000074
|
||||
#define RX_REO_QUEUE_1K_RESERVED_29_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RESERVED_29_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RESERVED_29_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RESERVED_30_OFFSET 0x00000078
|
||||
#define RX_REO_QUEUE_1K_RESERVED_30_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RESERVED_30_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RESERVED_30_MASK 0xffffffff
|
||||
|
||||
#define RX_REO_QUEUE_1K_RESERVED_31_OFFSET 0x0000007c
|
||||
#define RX_REO_QUEUE_1K_RESERVED_31_LSB 0
|
||||
#define RX_REO_QUEUE_1K_RESERVED_31_MSB 31
|
||||
#define RX_REO_QUEUE_1K_RESERVED_31_MASK 0xffffffff
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,900 @@
|
|||
/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
// $ATH_LICENSE_HW_HDR_C$
|
||||
//
|
||||
// DO NOT EDIT! This file is automatically generated
|
||||
// These definitions are tied to a particular hardware layout
|
||||
|
||||
|
||||
#ifndef _PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_H_
|
||||
#define _PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
|
||||
// ################ START SUMMARY #################
|
||||
//
|
||||
// Dword Fields
|
||||
// 0 number_of_symbols[15:0], nss_count[23:16], pilot_count[31:24]
|
||||
// 1 pilot_0_evm[31:0]
|
||||
// 2 pilot_1_evm[31:0]
|
||||
// 3 pilot_2_evm[31:0]
|
||||
// 4 pilot_3_evm[31:0]
|
||||
// 5 pilot_4_evm[31:0]
|
||||
// 6 pilot_5_evm[31:0]
|
||||
// 7 pilot_6_evm[31:0]
|
||||
// 8 pilot_7_evm[31:0]
|
||||
// 9 pilot_8_evm[31:0]
|
||||
// 10 pilot_9_evm[31:0]
|
||||
// 11 pilot_10_evm[31:0]
|
||||
// 12 pilot_11_evm[31:0]
|
||||
// 13 pilot_12_evm[31:0]
|
||||
// 14 pilot_13_evm[31:0]
|
||||
// 15 pilot_14_evm[31:0]
|
||||
// 16 pilot_15_evm[31:0]
|
||||
// 17 pilot_16_evm[31:0]
|
||||
// 18 pilot_17_evm[31:0]
|
||||
// 19 pilot_18_evm[31:0]
|
||||
// 20 pilot_19_evm[31:0]
|
||||
// 21 pilot_20_evm[31:0]
|
||||
// 22 pilot_21_evm[31:0]
|
||||
// 23 pilot_22_evm[31:0]
|
||||
// 24 pilot_23_evm[31:0]
|
||||
// 25 pilot_24_evm[31:0]
|
||||
// 26 pilot_25_evm[31:0]
|
||||
// 27 pilot_26_evm[31:0]
|
||||
// 28 pilot_27_evm[31:0]
|
||||
// 29 pilot_28_evm[31:0]
|
||||
// 30 pilot_29_evm[31:0]
|
||||
// 31 pilot_30_evm[31:0]
|
||||
// 32 pilot_31_evm[31:0]
|
||||
//
|
||||
// ################ END SUMMARY #################
|
||||
|
||||
#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS 33
|
||||
|
||||
struct phyrx_other_receive_info_su_evm_details {
|
||||
uint32_t number_of_symbols : 16, //[15:0]
|
||||
nss_count : 8, //[23:16]
|
||||
pilot_count : 8; //[31:24]
|
||||
uint32_t pilot_0_evm : 32; //[31:0]
|
||||
uint32_t pilot_1_evm : 32; //[31:0]
|
||||
uint32_t pilot_2_evm : 32; //[31:0]
|
||||
uint32_t pilot_3_evm : 32; //[31:0]
|
||||
uint32_t pilot_4_evm : 32; //[31:0]
|
||||
uint32_t pilot_5_evm : 32; //[31:0]
|
||||
uint32_t pilot_6_evm : 32; //[31:0]
|
||||
uint32_t pilot_7_evm : 32; //[31:0]
|
||||
uint32_t pilot_8_evm : 32; //[31:0]
|
||||
uint32_t pilot_9_evm : 32; //[31:0]
|
||||
uint32_t pilot_10_evm : 32; //[31:0]
|
||||
uint32_t pilot_11_evm : 32; //[31:0]
|
||||
uint32_t pilot_12_evm : 32; //[31:0]
|
||||
uint32_t pilot_13_evm : 32; //[31:0]
|
||||
uint32_t pilot_14_evm : 32; //[31:0]
|
||||
uint32_t pilot_15_evm : 32; //[31:0]
|
||||
uint32_t pilot_16_evm : 32; //[31:0]
|
||||
uint32_t pilot_17_evm : 32; //[31:0]
|
||||
uint32_t pilot_18_evm : 32; //[31:0]
|
||||
uint32_t pilot_19_evm : 32; //[31:0]
|
||||
uint32_t pilot_20_evm : 32; //[31:0]
|
||||
uint32_t pilot_21_evm : 32; //[31:0]
|
||||
uint32_t pilot_22_evm : 32; //[31:0]
|
||||
uint32_t pilot_23_evm : 32; //[31:0]
|
||||
uint32_t pilot_24_evm : 32; //[31:0]
|
||||
uint32_t pilot_25_evm : 32; //[31:0]
|
||||
uint32_t pilot_26_evm : 32; //[31:0]
|
||||
uint32_t pilot_27_evm : 32; //[31:0]
|
||||
uint32_t pilot_28_evm : 32; //[31:0]
|
||||
uint32_t pilot_29_evm : 32; //[31:0]
|
||||
uint32_t pilot_30_evm : 32; //[31:0]
|
||||
uint32_t pilot_31_evm : 32; //[31:0]
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
number_of_symbols
|
||||
|
||||
The number of symbols over which this EVM measurement
|
||||
was done
|
||||
|
||||
<legal all>
|
||||
|
||||
nss_count
|
||||
|
||||
The number of Spatial Streams in this SU reception.
|
||||
|
||||
<legal 1-8>
|
||||
|
||||
pilot_count
|
||||
|
||||
The number of pilots captured per Spatial Stream in this
|
||||
log
|
||||
|
||||
<legal 1-32>
|
||||
|
||||
pilot_0_evm
|
||||
|
||||
|
||||
|
||||
|
||||
Example mapping of Nss and pilots to the evm fields:
|
||||
|
||||
With NSS_count = 2, Pilot_count = 3
|
||||
|
||||
Pilot_0_evm => NSS 0, Pilot 0
|
||||
|
||||
Pilot_1_evm => NSS 1, Pilot 0
|
||||
|
||||
Pilot_2_evm => NSS 0, Pilot 1
|
||||
|
||||
Pilot_3_evm => NSS 1, Pilot 1
|
||||
|
||||
Pilot_4_evm => NSS 0, Pilot 2
|
||||
|
||||
Pilot_5_evm => NSS 1, Pilot 2
|
||||
|
||||
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_1_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_2_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_3_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_4_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_5_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_6_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_7_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_8_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_9_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_10_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_11_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_12_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_13_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_14_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_15_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_16_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_17_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_18_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_19_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_20_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_21_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_22_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_23_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_24_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_25_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_26_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_27_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_28_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_29_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_30_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
|
||||
pilot_31_evm
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS
|
||||
|
||||
The number of symbols over which this EVM measurement
|
||||
was done
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS_OFFSET 0x00000000
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS_MASK 0x0000ffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NSS_COUNT
|
||||
|
||||
The number of Spatial Streams in this SU reception.
|
||||
|
||||
<legal 1-8>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NSS_COUNT_OFFSET 0x00000000
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NSS_COUNT_LSB 16
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NSS_COUNT_MASK 0x00ff0000
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_PILOT_COUNT
|
||||
|
||||
The number of pilots captured per Spatial Stream in this
|
||||
log
|
||||
|
||||
<legal 1-32>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_PILOT_COUNT_OFFSET 0x00000000
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_PILOT_COUNT_LSB 24
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_PILOT_COUNT_MASK 0xff000000
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_1_PILOT_0_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
Example mapping of Nss and pilots to the evm fields:
|
||||
|
||||
With NSS_count = 2, Pilot_count = 3
|
||||
|
||||
Pilot_0_evm => NSS 0, Pilot 0
|
||||
|
||||
Pilot_1_evm => NSS 1, Pilot 0
|
||||
|
||||
Pilot_2_evm => NSS 0, Pilot 1
|
||||
|
||||
Pilot_3_evm => NSS 1, Pilot 1
|
||||
|
||||
Pilot_4_evm => NSS 0, Pilot 2
|
||||
|
||||
Pilot_5_evm => NSS 1, Pilot 2
|
||||
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_1_PILOT_0_EVM_OFFSET 0x00000004
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_1_PILOT_0_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_1_PILOT_0_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_2_PILOT_1_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_2_PILOT_1_EVM_OFFSET 0x00000008
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_2_PILOT_1_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_2_PILOT_1_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_3_PILOT_2_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_3_PILOT_2_EVM_OFFSET 0x0000000c
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_3_PILOT_2_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_3_PILOT_2_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_4_PILOT_3_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_4_PILOT_3_EVM_OFFSET 0x00000010
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_4_PILOT_3_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_4_PILOT_3_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_5_PILOT_4_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_5_PILOT_4_EVM_OFFSET 0x00000014
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_5_PILOT_4_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_5_PILOT_4_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_6_PILOT_5_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_6_PILOT_5_EVM_OFFSET 0x00000018
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_6_PILOT_5_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_6_PILOT_5_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_7_PILOT_6_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_7_PILOT_6_EVM_OFFSET 0x0000001c
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_7_PILOT_6_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_7_PILOT_6_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_8_PILOT_7_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_8_PILOT_7_EVM_OFFSET 0x00000020
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_8_PILOT_7_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_8_PILOT_7_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_9_PILOT_8_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_9_PILOT_8_EVM_OFFSET 0x00000024
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_9_PILOT_8_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_9_PILOT_8_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_10_PILOT_9_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_10_PILOT_9_EVM_OFFSET 0x00000028
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_10_PILOT_9_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_10_PILOT_9_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_11_PILOT_10_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_11_PILOT_10_EVM_OFFSET 0x0000002c
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_11_PILOT_10_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_11_PILOT_10_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_12_PILOT_11_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_12_PILOT_11_EVM_OFFSET 0x00000030
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_12_PILOT_11_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_12_PILOT_11_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_13_PILOT_12_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_13_PILOT_12_EVM_OFFSET 0x00000034
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_13_PILOT_12_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_13_PILOT_12_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_14_PILOT_13_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_14_PILOT_13_EVM_OFFSET 0x00000038
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_14_PILOT_13_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_14_PILOT_13_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_15_PILOT_14_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_15_PILOT_14_EVM_OFFSET 0x0000003c
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_15_PILOT_14_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_15_PILOT_14_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_16_PILOT_15_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_16_PILOT_15_EVM_OFFSET 0x00000040
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_16_PILOT_15_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_16_PILOT_15_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_17_PILOT_16_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_17_PILOT_16_EVM_OFFSET 0x00000044
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_17_PILOT_16_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_17_PILOT_16_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_18_PILOT_17_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_18_PILOT_17_EVM_OFFSET 0x00000048
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_18_PILOT_17_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_18_PILOT_17_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_19_PILOT_18_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_19_PILOT_18_EVM_OFFSET 0x0000004c
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_19_PILOT_18_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_19_PILOT_18_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_20_PILOT_19_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_20_PILOT_19_EVM_OFFSET 0x00000050
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_20_PILOT_19_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_20_PILOT_19_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_21_PILOT_20_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_21_PILOT_20_EVM_OFFSET 0x00000054
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_21_PILOT_20_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_21_PILOT_20_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_22_PILOT_21_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_22_PILOT_21_EVM_OFFSET 0x00000058
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_22_PILOT_21_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_22_PILOT_21_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_23_PILOT_22_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_23_PILOT_22_EVM_OFFSET 0x0000005c
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_23_PILOT_22_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_23_PILOT_22_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_24_PILOT_23_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_24_PILOT_23_EVM_OFFSET 0x00000060
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_24_PILOT_23_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_24_PILOT_23_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_25_PILOT_24_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_25_PILOT_24_EVM_OFFSET 0x00000064
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_25_PILOT_24_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_25_PILOT_24_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_26_PILOT_25_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_26_PILOT_25_EVM_OFFSET 0x00000068
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_26_PILOT_25_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_26_PILOT_25_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_27_PILOT_26_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_27_PILOT_26_EVM_OFFSET 0x0000006c
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_27_PILOT_26_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_27_PILOT_26_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_28_PILOT_27_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_28_PILOT_27_EVM_OFFSET 0x00000070
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_28_PILOT_27_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_28_PILOT_27_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_29_PILOT_28_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_29_PILOT_28_EVM_OFFSET 0x00000074
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_29_PILOT_28_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_29_PILOT_28_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_30_PILOT_29_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_30_PILOT_29_EVM_OFFSET 0x00000078
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_30_PILOT_29_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_30_PILOT_29_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_31_PILOT_30_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_31_PILOT_30_EVM_OFFSET 0x0000007c
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_31_PILOT_30_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_31_PILOT_30_EVM_MASK 0xffffffff
|
||||
|
||||
/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_32_PILOT_31_EVM
|
||||
|
||||
|
||||
|
||||
|
||||
See Pilot_0_evm descriptions details for mapping info
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_32_PILOT_31_EVM_OFFSET 0x00000080
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_32_PILOT_31_EVM_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_32_PILOT_31_EVM_MASK 0xffffffff
|
||||
|
||||
|
||||
#endif // _PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_H_
|
||||
1901
drivers/staging/fw-api/hw/qca8074/v2/phyrx_pkt_end_info.h
Normal file
1901
drivers/staging/fw-api/hw/qca8074/v2/phyrx_pkt_end_info.h
Normal file
File diff suppressed because it is too large
Load diff
1181
drivers/staging/fw-api/hw/qca8074/v2/reo_entrance_ring.h
Normal file
1181
drivers/staging/fw-api/hw/qca8074/v2/reo_entrance_ring.h
Normal file
File diff suppressed because it is too large
Load diff
16
drivers/staging/fw-api/hw/qca8074/v2/wcss_version.h
Normal file
16
drivers/staging/fw-api/hw/qca8074/v2/wcss_version.h
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#define WCSS_VERSION 1057
|
||||
94
drivers/staging/fw-api/hw/qcn9224/v1/ack_report.h
Normal file
94
drivers/staging/fw-api/hw/qcn9224/v1/ack_report.h
Normal file
|
|
@ -0,0 +1,94 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef _ACK_REPORT_H_
|
||||
#define _ACK_REPORT_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_ACK_REPORT 1
|
||||
|
||||
|
||||
struct ack_report {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t selfgen_response_reason : 4, // [3:0]
|
||||
ax_trigger_type : 4, // [7:4]
|
||||
sr_ppdu : 1, // [8:8]
|
||||
reserved : 7, // [15:9]
|
||||
frame_control : 16; // [31:16]
|
||||
#else
|
||||
uint32_t frame_control : 16, // [31:16]
|
||||
reserved : 7, // [15:9]
|
||||
sr_ppdu : 1, // [8:8]
|
||||
ax_trigger_type : 4, // [7:4]
|
||||
selfgen_response_reason : 4; // [3:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000
|
||||
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0
|
||||
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3
|
||||
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f
|
||||
|
||||
|
||||
|
||||
|
||||
#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000
|
||||
#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4
|
||||
#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7
|
||||
#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0
|
||||
|
||||
|
||||
|
||||
|
||||
#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000
|
||||
#define ACK_REPORT_SR_PPDU_LSB 8
|
||||
#define ACK_REPORT_SR_PPDU_MSB 8
|
||||
#define ACK_REPORT_SR_PPDU_MASK 0x00000100
|
||||
|
||||
|
||||
|
||||
|
||||
#define ACK_REPORT_RESERVED_OFFSET 0x00000000
|
||||
#define ACK_REPORT_RESERVED_LSB 9
|
||||
#define ACK_REPORT_RESERVED_MSB 15
|
||||
#define ACK_REPORT_RESERVED_MASK 0x0000fe00
|
||||
|
||||
|
||||
|
||||
|
||||
#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000
|
||||
#define ACK_REPORT_FRAME_CONTROL_LSB 16
|
||||
#define ACK_REPORT_FRAME_CONTROL_MSB 31
|
||||
#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
154
drivers/staging/fw-api/hw/qcn9224/v1/eht_sig_usr_mu_mimo_info.h
Normal file
154
drivers/staging/fw-api/hw/qcn9224/v1/eht_sig_usr_mu_mimo_info.h
Normal file
|
|
@ -0,0 +1,154 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_
|
||||
#define _EHT_SIG_USR_MU_MIMO_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2
|
||||
|
||||
|
||||
struct eht_sig_usr_mu_mimo_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t sta_id : 11, // [10:0]
|
||||
sta_mcs : 4, // [14:11]
|
||||
sta_coding : 1, // [15:15]
|
||||
sta_spatial_config : 6, // [21:16]
|
||||
reserved_0a : 1, // [22:22]
|
||||
rx_integrity_check_passed : 1, // [23:23]
|
||||
subband80_cc_mask : 8; // [31:24]
|
||||
uint32_t user_order_subband80_0 : 8, // [7:0]
|
||||
user_order_subband80_1 : 8, // [15:8]
|
||||
user_order_subband80_2 : 8, // [23:16]
|
||||
user_order_subband80_3 : 8; // [31:24]
|
||||
#else
|
||||
uint32_t subband80_cc_mask : 8, // [31:24]
|
||||
rx_integrity_check_passed : 1, // [23:23]
|
||||
reserved_0a : 1, // [22:22]
|
||||
sta_spatial_config : 6, // [21:16]
|
||||
sta_coding : 1, // [15:15]
|
||||
sta_mcs : 4, // [14:11]
|
||||
sta_id : 11; // [10:0]
|
||||
uint32_t user_order_subband80_3 : 8, // [31:24]
|
||||
user_order_subband80_2 : 8, // [23:16]
|
||||
user_order_subband80_1 : 8, // [15:8]
|
||||
user_order_subband80_0 : 8; // [7:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
174
drivers/staging/fw-api/hw/qcn9224/v1/eht_sig_usr_ofdma_info.h
Normal file
174
drivers/staging/fw-api/hw/qcn9224/v1/eht_sig_usr_ofdma_info.h
Normal file
|
|
@ -0,0 +1,174 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef _EHT_SIG_USR_OFDMA_INFO_H_
|
||||
#define _EHT_SIG_USR_OFDMA_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2
|
||||
|
||||
|
||||
struct eht_sig_usr_ofdma_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t sta_id : 11, // [10:0]
|
||||
sta_mcs : 4, // [14:11]
|
||||
validate_0a : 1, // [15:15]
|
||||
nss : 4, // [19:16]
|
||||
txbf : 1, // [20:20]
|
||||
sta_coding : 1, // [21:21]
|
||||
reserved_0b : 1, // [22:22]
|
||||
rx_integrity_check_passed : 1, // [23:23]
|
||||
subband80_cc_mask : 8; // [31:24]
|
||||
uint32_t user_order_subband80_0 : 8, // [7:0]
|
||||
user_order_subband80_1 : 8, // [15:8]
|
||||
user_order_subband80_2 : 8, // [23:16]
|
||||
user_order_subband80_3 : 8; // [31:24]
|
||||
#else
|
||||
uint32_t subband80_cc_mask : 8, // [31:24]
|
||||
rx_integrity_check_passed : 1, // [23:23]
|
||||
reserved_0b : 1, // [22:22]
|
||||
sta_coding : 1, // [21:21]
|
||||
txbf : 1, // [20:20]
|
||||
nss : 4, // [19:16]
|
||||
validate_0a : 1, // [15:15]
|
||||
sta_mcs : 4, // [14:11]
|
||||
sta_id : 11; // [10:0]
|
||||
uint32_t user_order_subband80_3 : 8, // [31:24]
|
||||
user_order_subband80_2 : 8, // [23:16]
|
||||
user_order_subband80_1 : 8, // [15:8]
|
||||
user_order_subband80_0 : 8; // [7:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15
|
||||
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15
|
||||
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16
|
||||
#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19
|
||||
#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20
|
||||
#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20
|
||||
#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24
|
||||
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31
|
||||
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
124
drivers/staging/fw-api/hw/qcn9224/v1/eht_sig_usr_su_info.h
Normal file
124
drivers/staging/fw-api/hw/qcn9224/v1/eht_sig_usr_su_info.h
Normal file
|
|
@ -0,0 +1,124 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef _EHT_SIG_USR_SU_INFO_H_
|
||||
#define _EHT_SIG_USR_SU_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1
|
||||
|
||||
|
||||
struct eht_sig_usr_su_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t sta_id : 11, // [10:0]
|
||||
sta_mcs : 4, // [14:11]
|
||||
validate_0a : 1, // [15:15]
|
||||
nss : 4, // [19:16]
|
||||
txbf : 1, // [20:20]
|
||||
sta_coding : 1, // [21:21]
|
||||
reserved_0b : 9, // [30:22]
|
||||
rx_integrity_check_passed : 1; // [31:31]
|
||||
#else
|
||||
uint32_t rx_integrity_check_passed : 1, // [31:31]
|
||||
reserved_0b : 9, // [30:22]
|
||||
sta_coding : 1, // [21:21]
|
||||
txbf : 1, // [20:20]
|
||||
nss : 4, // [19:16]
|
||||
validate_0a : 1, // [15:15]
|
||||
sta_mcs : 4, // [14:11]
|
||||
sta_id : 11; // [10:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0
|
||||
#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10
|
||||
#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11
|
||||
#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14
|
||||
#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15
|
||||
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15
|
||||
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_NSS_LSB 16
|
||||
#define EHT_SIG_USR_SU_INFO_NSS_MSB 19
|
||||
#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20
|
||||
#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20
|
||||
#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21
|
||||
#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21
|
||||
#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22
|
||||
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30
|
||||
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000
|
||||
|
||||
|
||||
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
164
drivers/staging/fw-api/hw/qcn9224/v1/he_sig_a_mu_ul_info.h
Normal file
164
drivers/staging/fw-api/hw/qcn9224/v1/he_sig_a_mu_ul_info.h
Normal file
|
|
@ -0,0 +1,164 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef _HE_SIG_A_MU_UL_INFO_H_
|
||||
#define _HE_SIG_A_MU_UL_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2
|
||||
|
||||
|
||||
struct he_sig_a_mu_ul_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t format_indication : 1, // [0:0]
|
||||
bss_color_id : 6, // [6:1]
|
||||
spatial_reuse : 16, // [22:7]
|
||||
reserved_0a : 1, // [23:23]
|
||||
transmit_bw : 2, // [25:24]
|
||||
reserved_0b : 6; // [31:26]
|
||||
uint32_t txop_duration : 7, // [6:0]
|
||||
reserved_1a : 9, // [15:7]
|
||||
crc : 4, // [19:16]
|
||||
tail : 6, // [25:20]
|
||||
reserved_1b : 5, // [30:26]
|
||||
rx_integrity_check_passed : 1; // [31:31]
|
||||
#else
|
||||
uint32_t reserved_0b : 6, // [31:26]
|
||||
transmit_bw : 2, // [25:24]
|
||||
reserved_0a : 1, // [23:23]
|
||||
spatial_reuse : 16, // [22:7]
|
||||
bss_color_id : 6, // [6:1]
|
||||
format_indication : 1; // [0:0]
|
||||
uint32_t rx_integrity_check_passed : 1, // [31:31]
|
||||
reserved_1b : 5, // [30:26]
|
||||
tail : 6, // [25:20]
|
||||
crc : 4, // [19:16]
|
||||
reserved_1a : 9, // [15:7]
|
||||
txop_duration : 7; // [6:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0
|
||||
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0
|
||||
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001
|
||||
|
||||
|
||||
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1
|
||||
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6
|
||||
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e
|
||||
|
||||
|
||||
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7
|
||||
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22
|
||||
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80
|
||||
|
||||
|
||||
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000
|
||||
|
||||
|
||||
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24
|
||||
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25
|
||||
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0
|
||||
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6
|
||||
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f
|
||||
|
||||
|
||||
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80
|
||||
|
||||
|
||||
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16
|
||||
#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19
|
||||
#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000
|
||||
|
||||
|
||||
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20
|
||||
#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25
|
||||
#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000
|
||||
|
||||
|
||||
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
174
drivers/staging/fw-api/hw/qcn9224/v1/no_ack_report.h
Normal file
174
drivers/staging/fw-api/hw/qcn9224/v1/no_ack_report.h
Normal file
|
|
@ -0,0 +1,174 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef _NO_ACK_REPORT_H_
|
||||
#define _NO_ACK_REPORT_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_NO_ACK_REPORT 4
|
||||
|
||||
|
||||
struct no_ack_report {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t no_ack_transmit_reason : 4, // [3:0]
|
||||
macrx_abort_reason : 4, // [7:4]
|
||||
phyrx_abort_reason : 8, // [15:8]
|
||||
frame_control : 16; // [31:16]
|
||||
uint32_t rx_ppdu_duration : 24, // [23:0]
|
||||
sr_ppdu_during_obss : 1, // [24:24]
|
||||
selfgen_response_reason_to_sr_ppdu : 4, // [28:25]
|
||||
reserved_1 : 3; // [31:29]
|
||||
uint32_t pre_bt_broadcast_status_details : 12, // [11:0]
|
||||
first_bt_broadcast_status_details : 12, // [23:12]
|
||||
reserved_2 : 8; // [31:24]
|
||||
uint32_t second_bt_broadcast_status_details : 12, // [11:0]
|
||||
reserved_3 : 20; // [31:12]
|
||||
#else
|
||||
uint32_t frame_control : 16, // [31:16]
|
||||
phyrx_abort_reason : 8, // [15:8]
|
||||
macrx_abort_reason : 4, // [7:4]
|
||||
no_ack_transmit_reason : 4; // [3:0]
|
||||
uint32_t reserved_1 : 3, // [31:29]
|
||||
selfgen_response_reason_to_sr_ppdu : 4, // [28:25]
|
||||
sr_ppdu_during_obss : 1, // [24:24]
|
||||
rx_ppdu_duration : 24; // [23:0]
|
||||
uint32_t reserved_2 : 8, // [31:24]
|
||||
first_bt_broadcast_status_details : 12, // [23:12]
|
||||
pre_bt_broadcast_status_details : 12; // [11:0]
|
||||
uint32_t reserved_3 : 20, // [31:12]
|
||||
second_bt_broadcast_status_details : 12; // [11:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000
|
||||
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0
|
||||
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3
|
||||
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f
|
||||
|
||||
|
||||
|
||||
|
||||
#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000
|
||||
#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4
|
||||
#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7
|
||||
#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0
|
||||
|
||||
|
||||
|
||||
|
||||
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000
|
||||
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8
|
||||
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15
|
||||
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00
|
||||
|
||||
|
||||
|
||||
|
||||
#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000
|
||||
#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16
|
||||
#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31
|
||||
#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000
|
||||
|
||||
|
||||
|
||||
|
||||
#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004
|
||||
#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0
|
||||
#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23
|
||||
#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff
|
||||
|
||||
|
||||
|
||||
|
||||
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004
|
||||
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24
|
||||
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24
|
||||
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004
|
||||
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25
|
||||
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28
|
||||
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004
|
||||
#define NO_ACK_REPORT_RESERVED_1_LSB 29
|
||||
#define NO_ACK_REPORT_RESERVED_1_MSB 31
|
||||
#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008
|
||||
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0
|
||||
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11
|
||||
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff
|
||||
|
||||
|
||||
|
||||
|
||||
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008
|
||||
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12
|
||||
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23
|
||||
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000
|
||||
|
||||
|
||||
|
||||
|
||||
#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008
|
||||
#define NO_ACK_REPORT_RESERVED_2_LSB 24
|
||||
#define NO_ACK_REPORT_RESERVED_2_MSB 31
|
||||
#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c
|
||||
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0
|
||||
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11
|
||||
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff
|
||||
|
||||
|
||||
|
||||
|
||||
#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c
|
||||
#define NO_ACK_REPORT_RESERVED_3_LSB 12
|
||||
#define NO_ACK_REPORT_RESERVED_3_MSB 31
|
||||
#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
597
drivers/staging/fw-api/hw/qcn9224/v1/pdg_response_rate_setting.h
Normal file
597
drivers/staging/fw-api/hw/qcn9224/v1/pdg_response_rate_setting.h
Normal file
|
|
@ -0,0 +1,597 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef _PDG_RESPONSE_RATE_SETTING_H_
|
||||
#define _PDG_RESPONSE_RATE_SETTING_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "mlo_sta_id_details.h"
|
||||
#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7
|
||||
|
||||
|
||||
struct pdg_response_rate_setting {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t reserved_0a : 1, // [0:0]
|
||||
tx_antenna_sector_ctrl : 24, // [24:1]
|
||||
pkt_type : 4, // [28:25]
|
||||
smoothing : 1, // [29:29]
|
||||
ldpc : 1, // [30:30]
|
||||
stbc : 1; // [31:31]
|
||||
uint32_t alt_tx_pwr : 8, // [7:0]
|
||||
alt_min_tx_pwr : 8, // [15:8]
|
||||
alt_nss : 3, // [18:16]
|
||||
alt_tx_chain_mask : 8, // [26:19]
|
||||
alt_bw : 3, // [29:27]
|
||||
stf_ltf_3db_boost : 1, // [30:30]
|
||||
force_extra_symbol : 1; // [31:31]
|
||||
uint32_t alt_rate_mcs : 4, // [3:0]
|
||||
nss : 3, // [6:4]
|
||||
dpd_enable : 1, // [7:7]
|
||||
tx_pwr : 8, // [15:8]
|
||||
min_tx_pwr : 8, // [23:16]
|
||||
tx_chain_mask : 8; // [31:24]
|
||||
uint32_t reserved_3a : 8, // [7:0]
|
||||
sgi : 2, // [9:8]
|
||||
rate_mcs : 4, // [13:10]
|
||||
reserved_3b : 2, // [15:14]
|
||||
tx_pwr_1 : 8, // [23:16]
|
||||
alt_tx_pwr_1 : 8; // [31:24]
|
||||
uint32_t aggregation : 1, // [0:0]
|
||||
dot11ax_bss_color_id : 6, // [6:1]
|
||||
dot11ax_spatial_reuse : 4, // [10:7]
|
||||
dot11ax_cp_ltf_size : 2, // [12:11]
|
||||
dot11ax_dcm : 1, // [13:13]
|
||||
dot11ax_doppler_indication : 1, // [14:14]
|
||||
dot11ax_su_extended : 1, // [15:15]
|
||||
dot11ax_min_packet_extension : 2, // [17:16]
|
||||
dot11ax_pe_nss : 3, // [20:18]
|
||||
dot11ax_pe_content : 1, // [21:21]
|
||||
dot11ax_pe_ltf_size : 2, // [23:22]
|
||||
dot11ax_chain_csd_en : 1, // [24:24]
|
||||
dot11ax_pe_chain_csd_en : 1, // [25:25]
|
||||
dot11ax_dl_ul_flag : 1, // [26:26]
|
||||
reserved_4a : 5; // [31:27]
|
||||
uint32_t dot11ax_ext_ru_start_index : 4, // [3:0]
|
||||
dot11ax_ext_ru_size : 4, // [7:4]
|
||||
eht_duplicate_mode : 2, // [9:8]
|
||||
he_sigb_dcm : 1, // [10:10]
|
||||
he_sigb_0_mcs : 3, // [13:11]
|
||||
num_he_sigb_sym : 5, // [18:14]
|
||||
required_response_time_source : 1, // [19:19]
|
||||
reserved_5a : 6, // [25:20]
|
||||
u_sig_puncture_pattern_encoding : 6; // [31:26]
|
||||
struct mlo_sta_id_details mlo_sta_id_details_rx;
|
||||
uint16_t required_response_time : 12, // [27:16]
|
||||
dot11be_params_placeholder : 4; // [31:28]
|
||||
#else
|
||||
uint32_t stbc : 1, // [31:31]
|
||||
ldpc : 1, // [30:30]
|
||||
smoothing : 1, // [29:29]
|
||||
pkt_type : 4, // [28:25]
|
||||
tx_antenna_sector_ctrl : 24, // [24:1]
|
||||
reserved_0a : 1; // [0:0]
|
||||
uint32_t force_extra_symbol : 1, // [31:31]
|
||||
stf_ltf_3db_boost : 1, // [30:30]
|
||||
alt_bw : 3, // [29:27]
|
||||
alt_tx_chain_mask : 8, // [26:19]
|
||||
alt_nss : 3, // [18:16]
|
||||
alt_min_tx_pwr : 8, // [15:8]
|
||||
alt_tx_pwr : 8; // [7:0]
|
||||
uint32_t tx_chain_mask : 8, // [31:24]
|
||||
min_tx_pwr : 8, // [23:16]
|
||||
tx_pwr : 8, // [15:8]
|
||||
dpd_enable : 1, // [7:7]
|
||||
nss : 3, // [6:4]
|
||||
alt_rate_mcs : 4; // [3:0]
|
||||
uint32_t alt_tx_pwr_1 : 8, // [31:24]
|
||||
tx_pwr_1 : 8, // [23:16]
|
||||
reserved_3b : 2, // [15:14]
|
||||
rate_mcs : 4, // [13:10]
|
||||
sgi : 2, // [9:8]
|
||||
reserved_3a : 8; // [7:0]
|
||||
uint32_t reserved_4a : 5, // [31:27]
|
||||
dot11ax_dl_ul_flag : 1, // [26:26]
|
||||
dot11ax_pe_chain_csd_en : 1, // [25:25]
|
||||
dot11ax_chain_csd_en : 1, // [24:24]
|
||||
dot11ax_pe_ltf_size : 2, // [23:22]
|
||||
dot11ax_pe_content : 1, // [21:21]
|
||||
dot11ax_pe_nss : 3, // [20:18]
|
||||
dot11ax_min_packet_extension : 2, // [17:16]
|
||||
dot11ax_su_extended : 1, // [15:15]
|
||||
dot11ax_doppler_indication : 1, // [14:14]
|
||||
dot11ax_dcm : 1, // [13:13]
|
||||
dot11ax_cp_ltf_size : 2, // [12:11]
|
||||
dot11ax_spatial_reuse : 4, // [10:7]
|
||||
dot11ax_bss_color_id : 6, // [6:1]
|
||||
aggregation : 1; // [0:0]
|
||||
uint32_t u_sig_puncture_pattern_encoding : 6, // [31:26]
|
||||
reserved_5a : 6, // [25:20]
|
||||
required_response_time_source : 1, // [19:19]
|
||||
num_he_sigb_sym : 5, // [18:14]
|
||||
he_sigb_0_mcs : 3, // [13:11]
|
||||
he_sigb_dcm : 1, // [10:10]
|
||||
eht_duplicate_mode : 2, // [9:8]
|
||||
dot11ax_ext_ru_size : 4, // [7:4]
|
||||
dot11ax_ext_ru_start_index : 4; // [3:0]
|
||||
uint32_t dot11be_params_placeholder : 4, // [31:28]
|
||||
required_response_time : 12; // [27:16]
|
||||
struct mlo_sta_id_details mlo_sta_id_details_rx;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25
|
||||
#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28
|
||||
#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29
|
||||
#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29
|
||||
#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30
|
||||
#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30
|
||||
#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30
|
||||
#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30
|
||||
#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 3
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000000f
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4
|
||||
#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6
|
||||
#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7
|
||||
#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7
|
||||
#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16
|
||||
#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23
|
||||
#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000ff
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8
|
||||
#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9
|
||||
#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10
|
||||
#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 13
|
||||
#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00003c00
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_LSB 14
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MSB 15
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MASK 0x0000c000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8
|
||||
#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9
|
||||
#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14
|
||||
#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18
|
||||
#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
|
||||
#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
|
||||
|
||||
|
||||
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef _PHYTX_ABORT_REQUEST_INFO_H_
|
||||
#define _PHYTX_ABORT_REQUEST_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1
|
||||
|
||||
|
||||
struct phytx_abort_request_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint16_t phytx_abort_reason : 8, // [7:0]
|
||||
user_number : 6, // [13:8]
|
||||
reserved : 2; // [15:14]
|
||||
#else
|
||||
uint16_t reserved : 2, // [15:14]
|
||||
user_number : 6, // [13:8]
|
||||
phytx_abort_reason : 8; // [7:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000
|
||||
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0
|
||||
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7
|
||||
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff
|
||||
|
||||
|
||||
|
||||
|
||||
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000
|
||||
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8
|
||||
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13
|
||||
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00
|
||||
|
||||
|
||||
|
||||
|
||||
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000
|
||||
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14
|
||||
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15
|
||||
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
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Reference in a new issue