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[SPARC64]: Proper multi-core scheduling support.

Browse source 
The scheduling domain hierarchy is:

   all cpus -->
      cpus that share an instruction cache -->
          cpus that share an integer execution unit

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2007-06-04 17:01:39 -07:00 • committed by David S. Miller
commit f78eae2e6f
7 changed files with 89 additions and 5 deletions
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2
include/asm-sparc64/cpudata.h
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@ -31,7 +31,7 @@ typedef struct {
unsigned int ecache_size;
unsigned int ecache_line_size;
int core_id;
unsigned int __pad3;
int proc_id;
} cpuinfo_sparc;
DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);

1
include/asm-sparc64/smp.h
View file

@ -33,6 +33,7 @@ extern cpumask_t phys_cpu_present_map;
#define cpu_possible_map phys_cpu_present_map
extern cpumask_t cpu_sibling_map[NR_CPUS];
extern cpumask_t cpu_core_map[NR_CPUS];
/*
* General functions that each host system must provide.

13
include/asm-sparc64/topology.h
View file

@ -1,12 +1,19 @@
#ifndef _ASM_SPARC64_TOPOLOGY_H
#define _ASM_SPARC64_TOPOLOGY_H
#ifdef CONFIG_SMP
#include <asm/spitfire.h>
#define smt_capable() (tlb_type == hypervisor)
#define topology_physical_package_id(cpu) (cpu_data(cpu).proc_id)
#define topology_core_id(cpu) (cpu_data(cpu).core_id)
#define topology_core_siblings(cpu) (cpu_core_map[cpu])
#define topology_thread_siblings(cpu) (cpu_sibling_map[cpu])
#define mc_capable() (tlb_type == hypervisor)
#define smt_capable() (tlb_type == hypervisor)
#endif /* CONFIG_SMP */
#include <asm-generic/topology.h>
#define topology_core_id(cpu) (cpu_data(cpu).core_id)
#define topology_thread_siblings(cpu) (cpu_sibling_map[cpu])
#define cpu_coregroup_map(cpu) (cpu_core_map[cpu])
#endif /* _ASM_SPARC64_TOPOLOGY_H */