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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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[CPUFREQ] Move ARM Samsung cpufreq drivers to drivers/cpufreq/
According to discussion of the ARM arch subsystem migration, ARM cpufreq drivers move to drivers/cpufreq. So this patch adds Kconfig.arm for ARM like x86 and adds Samsung S5PV210 and EXYNOS4210 cpufreq driver compile in there. As a note, otherw will be moved. Cc: Dave Jones <[email protected]> Signed-off-by: Kukjin Kim <[email protected]> Signed-off-by: Dave Jones <[email protected]>
This commit is contained in:
Kukjin Kim
Dave Jones
parent
be2de99bea
commit
f7d770790f
7 changed files with 32 additions and 6 deletions
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@ -184,5 +184,10 @@ depends on X86
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source "drivers/cpufreq/Kconfig.x86"
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endmenu
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menu "ARM CPU frequency scaling drivers"
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depends on ARM
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source "drivers/cpufreq/Kconfig.arm"
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endmenu
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endif
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endmenu
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23
drivers/cpufreq/Kconfig.arm
Normal file
23
drivers/cpufreq/Kconfig.arm
Normal file
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@ -0,0 +1,23 @@
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#
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# ARM CPU Frequency scaling drivers
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#
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config ARM_S5PV210_CPUFREQ
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bool "Samsung S5PV210 and S5PC110"
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depends on CPU_S5PV210
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default y
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help
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This adds the CPUFreq driver for Samsung S5PV210 and
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S5PC110 SoCs.
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If in doubt, say N.
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config ARM_EXYNOS4210_CPUFREQ
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bool "Samsung EXYNOS4210"
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depends on CPU_EXYNOS4210
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default y
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help
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This adds the CPUFreq driver for Samsung EXYNOS4210
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SoC (S5PV310 or S5PC210).
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If in doubt, say N.
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@ -42,3 +42,5 @@ obj-$(CONFIG_X86_CPUFREQ_NFORCE2) += cpufreq-nforce2.o
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# ARM SoC drivers
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obj-$(CONFIG_UX500_SOC_DB8500) += db8500-cpufreq.o
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obj-$(CONFIG_CPU_FREQ_S3C64XX) += s3c64xx.o
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obj-$(CONFIG_ARM_S5PV210_CPUFREQ) += s5pv210-cpufreq.o
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obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o
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568
drivers/cpufreq/exynos4210-cpufreq.c
Normal file
568
drivers/cpufreq/exynos4210-cpufreq.c
Normal file
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@ -0,0 +1,568 @@
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/*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4 - CPU frequency scaling support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/regulator/consumer.h>
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#include <linux/cpufreq.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-mem.h>
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#include <plat/clock.h>
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#include <plat/pm.h>
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static struct clk *cpu_clk;
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static struct clk *moutcore;
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static struct clk *mout_mpll;
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static struct clk *mout_apll;
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static struct regulator *arm_regulator;
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static struct regulator *int_regulator;
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static struct cpufreq_freqs freqs;
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static unsigned int memtype;
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enum exynos4_memory_type {
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DDR2 = 4,
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LPDDR2,
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DDR3,
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};
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enum cpufreq_level_index {
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L0, L1, L2, L3, CPUFREQ_LEVEL_END,
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};
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static struct cpufreq_frequency_table exynos4_freq_table[] = {
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{L0, 1000*1000},
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{L1, 800*1000},
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{L2, 400*1000},
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{L3, 100*1000},
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{0, CPUFREQ_TABLE_END},
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};
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static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
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/*
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* Clock divider value for following
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* { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
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* DIVATB, DIVPCLK_DBG, DIVAPLL }
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*/
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/* ARM L0: 1000MHz */
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{ 0, 3, 7, 3, 3, 0, 1 },
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/* ARM L1: 800MHz */
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{ 0, 3, 7, 3, 3, 0, 1 },
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/* ARM L2: 400MHz */
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{ 0, 1, 3, 1, 3, 0, 1 },
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/* ARM L3: 100MHz */
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{ 0, 0, 1, 0, 3, 1, 1 },
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};
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static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
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/*
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* Clock divider value for following
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* { DIVCOPY, DIVHPM }
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*/
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/* ARM L0: 1000MHz */
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{ 3, 0 },
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/* ARM L1: 800MHz */
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{ 3, 0 },
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/* ARM L2: 400MHz */
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{ 3, 0 },
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/* ARM L3: 100MHz */
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{ 3, 0 },
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};
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static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = {
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/*
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* Clock divider value for following
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* { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
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* DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
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*/
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/* DMC L0: 400MHz */
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{ 3, 1, 1, 1, 1, 1, 3, 1 },
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/* DMC L1: 400MHz */
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{ 3, 1, 1, 1, 1, 1, 3, 1 },
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/* DMC L2: 266.7MHz */
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{ 7, 1, 1, 2, 1, 1, 3, 1 },
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/* DMC L3: 200MHz */
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{ 7, 1, 1, 3, 1, 1, 3, 1 },
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};
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static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = {
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/*
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* Clock divider value for following
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* { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
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*/
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/* ACLK200 L0: 200MHz */
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{ 3, 7, 4, 5, 1 },
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/* ACLK200 L1: 200MHz */
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{ 3, 7, 4, 5, 1 },
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/* ACLK200 L2: 160MHz */
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{ 4, 7, 5, 7, 1 },
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/* ACLK200 L3: 133.3MHz */
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{ 5, 7, 7, 7, 1 },
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};
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static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = {
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/*
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* Clock divider value for following
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* { DIVGDL/R, DIVGPL/R }
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*/
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/* ACLK_GDL/R L0: 200MHz */
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{ 3, 1 },
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/* ACLK_GDL/R L1: 200MHz */
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{ 3, 1 },
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/* ACLK_GDL/R L2: 160MHz */
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{ 4, 1 },
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/* ACLK_GDL/R L3: 133.3MHz */
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{ 5, 1 },
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};
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struct cpufreq_voltage_table {
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unsigned int index; /* any */
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unsigned int arm_volt; /* uV */
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unsigned int int_volt;
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};
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static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
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{
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.index = L0,
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.arm_volt = 1200000,
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.int_volt = 1100000,
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}, {
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.index = L1,
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.arm_volt = 1100000,
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.int_volt = 1100000,
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}, {
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.index = L2,
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.arm_volt = 1000000,
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.int_volt = 1000000,
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}, {
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.index = L3,
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.arm_volt = 900000,
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.int_volt = 1000000,
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},
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};
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static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
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/* APLL FOUT L0: 1000MHz */
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((250 << 16) | (6 << 8) | 1),
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/* APLL FOUT L1: 800MHz */
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((200 << 16) | (6 << 8) | 1),
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/* APLL FOUT L2 : 400MHz */
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((200 << 16) | (6 << 8) | 2),
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/* APLL FOUT L3: 100MHz */
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((200 << 16) | (6 << 8) | 4),
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};
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int exynos4_verify_speed(struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
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}
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unsigned int exynos4_getspeed(unsigned int cpu)
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{
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return clk_get_rate(cpu_clk) / 1000;
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}
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void exynos4_set_clkdiv(unsigned int div_index)
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{
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unsigned int tmp;
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/* Change Divider - CPU0 */
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tmp = __raw_readl(S5P_CLKDIV_CPU);
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tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK |
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S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK |
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S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK |
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S5P_CLKDIV_CPU0_APLL_MASK);
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tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
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(clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
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(clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
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(clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
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(clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
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(clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
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(clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_CPU);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STATCPU);
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} while (tmp & 0x1111111);
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/* Change Divider - CPU1 */
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tmp = __raw_readl(S5P_CLKDIV_CPU1);
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tmp &= ~((0x7 << 4) | 0x7);
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tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
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(clkdiv_cpu1[div_index][1] << 0));
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__raw_writel(tmp, S5P_CLKDIV_CPU1);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
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} while (tmp & 0x11);
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/* Change Divider - DMC0 */
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tmp = __raw_readl(S5P_CLKDIV_DMC0);
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tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK |
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S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK |
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S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK |
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S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK);
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tmp |= ((clkdiv_dmc0[div_index][0] << S5P_CLKDIV_DMC0_ACP_SHIFT) |
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(clkdiv_dmc0[div_index][1] << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
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(clkdiv_dmc0[div_index][2] << S5P_CLKDIV_DMC0_DPHY_SHIFT) |
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(clkdiv_dmc0[div_index][3] << S5P_CLKDIV_DMC0_DMC_SHIFT) |
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(clkdiv_dmc0[div_index][4] << S5P_CLKDIV_DMC0_DMCD_SHIFT) |
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(clkdiv_dmc0[div_index][5] << S5P_CLKDIV_DMC0_DMCP_SHIFT) |
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(clkdiv_dmc0[div_index][6] << S5P_CLKDIV_DMC0_COPY2_SHIFT) |
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(clkdiv_dmc0[div_index][7] << S5P_CLKDIV_DMC0_CORETI_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_DMC0);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
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} while (tmp & 0x11111111);
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/* Change Divider - TOP */
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tmp = __raw_readl(S5P_CLKDIV_TOP);
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tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK |
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S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK |
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S5P_CLKDIV_TOP_ONENAND_MASK);
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tmp |= ((clkdiv_top[div_index][0] << S5P_CLKDIV_TOP_ACLK200_SHIFT) |
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(clkdiv_top[div_index][1] << S5P_CLKDIV_TOP_ACLK100_SHIFT) |
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(clkdiv_top[div_index][2] << S5P_CLKDIV_TOP_ACLK160_SHIFT) |
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(clkdiv_top[div_index][3] << S5P_CLKDIV_TOP_ACLK133_SHIFT) |
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(clkdiv_top[div_index][4] << S5P_CLKDIV_TOP_ONENAND_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_TOP);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
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} while (tmp & 0x11111);
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/* Change Divider - LEFTBUS */
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tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
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tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
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tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
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(clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
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} while (tmp & 0x11);
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/* Change Divider - RIGHTBUS */
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tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
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tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
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tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
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(clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
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__raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
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} while (tmp & 0x11);
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}
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static void exynos4_set_apll(unsigned int index)
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{
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unsigned int tmp;
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/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
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clk_set_parent(moutcore, mout_mpll);
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do {
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tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
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>> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
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tmp &= 0x7;
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} while (tmp != 0x2);
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/* 2. Set APLL Lock time */
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__raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);
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/* 3. Change PLL PMS values */
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tmp = __raw_readl(S5P_APLL_CON0);
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tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
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tmp |= exynos4_apll_pms_table[index];
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__raw_writel(tmp, S5P_APLL_CON0);
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/* 4. wait_lock_time */
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do {
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tmp = __raw_readl(S5P_APLL_CON0);
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} while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));
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/* 5. MUX_CORE_SEL = APLL */
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clk_set_parent(moutcore, mout_apll);
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do {
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tmp = __raw_readl(S5P_CLKMUX_STATCPU);
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tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
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} while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
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}
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static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
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{
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unsigned int tmp;
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if (old_index > new_index) {
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/* The frequency changing to L0 needs to change apll */
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if (freqs.new == exynos4_freq_table[L0].frequency) {
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/* 1. Change the system clock divider values */
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exynos4_set_clkdiv(new_index);
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/* 2. Change the apll m,p,s value */
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exynos4_set_apll(new_index);
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} else {
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/* 1. Change the system clock divider values */
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exynos4_set_clkdiv(new_index);
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/* 2. Change just s value in apll m,p,s value */
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tmp = __raw_readl(S5P_APLL_CON0);
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tmp &= ~(0x7 << 0);
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tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
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__raw_writel(tmp, S5P_APLL_CON0);
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}
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}
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else if (old_index < new_index) {
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/* The frequency changing from L0 needs to change apll */
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if (freqs.old == exynos4_freq_table[L0].frequency) {
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/* 1. Change the apll m,p,s value */
|
||||
exynos4_set_apll(new_index);
|
||||
|
||||
/* 2. Change the system clock divider values */
|
||||
exynos4_set_clkdiv(new_index);
|
||||
} else {
|
||||
/* 1. Change just s value in apll m,p,s value */
|
||||
tmp = __raw_readl(S5P_APLL_CON0);
|
||||
tmp &= ~(0x7 << 0);
|
||||
tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
|
||||
__raw_writel(tmp, S5P_APLL_CON0);
|
||||
|
||||
/* 2. Change the system clock divider values */
|
||||
exynos4_set_clkdiv(new_index);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int exynos4_target(struct cpufreq_policy *policy,
|
||||
unsigned int target_freq,
|
||||
unsigned int relation)
|
||||
{
|
||||
unsigned int index, old_index;
|
||||
unsigned int arm_volt, int_volt;
|
||||
|
||||
freqs.old = exynos4_getspeed(policy->cpu);
|
||||
|
||||
if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
|
||||
freqs.old, relation, &old_index))
|
||||
return -EINVAL;
|
||||
|
||||
if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
|
||||
target_freq, relation, &index))
|
||||
return -EINVAL;
|
||||
|
||||
freqs.new = exynos4_freq_table[index].frequency;
|
||||
freqs.cpu = policy->cpu;
|
||||
|
||||
if (freqs.new == freqs.old)
|
||||
return 0;
|
||||
|
||||
/* get the voltage value */
|
||||
arm_volt = exynos4_volt_table[index].arm_volt;
|
||||
int_volt = exynos4_volt_table[index].int_volt;
|
||||
|
||||
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
|
||||
|
||||
/* control regulator */
|
||||
if (freqs.new > freqs.old) {
|
||||
/* Voltage up */
|
||||
regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
|
||||
regulator_set_voltage(int_regulator, int_volt, int_volt);
|
||||
}
|
||||
|
||||
/* Clock Configuration Procedure */
|
||||
exynos4_set_frequency(old_index, index);
|
||||
|
||||
/* control regulator */
|
||||
if (freqs.new < freqs.old) {
|
||||
/* Voltage down */
|
||||
regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
|
||||
regulator_set_voltage(int_regulator, int_volt, int_volt);
|
||||
}
|
||||
|
||||
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
|
||||
{
|
||||
policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);
|
||||
|
||||
cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
|
||||
|
||||
/* set the transition latency value */
|
||||
policy->cpuinfo.transition_latency = 100000;
|
||||
|
||||
/*
|
||||
* EXYNOS4 multi-core processors has 2 cores
|
||||
* that the frequency cannot be set independently.
|
||||
* Each cpu is bound to the same speed.
|
||||
* So the affected cpu is all of the cpus.
|
||||
*/
|
||||
cpumask_setall(policy->cpus);
|
||||
|
||||
return cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
|
||||
}
|
||||
|
||||
static struct cpufreq_driver exynos4_driver = {
|
||||
.flags = CPUFREQ_STICKY,
|
||||
.verify = exynos4_verify_speed,
|
||||
.target = exynos4_target,
|
||||
.get = exynos4_getspeed,
|
||||
.init = exynos4_cpufreq_cpu_init,
|
||||
.name = "exynos4_cpufreq",
|
||||
#ifdef CONFIG_PM
|
||||
.suspend = exynos4_cpufreq_suspend,
|
||||
.resume = exynos4_cpufreq_resume,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int __init exynos4_cpufreq_init(void)
|
||||
{
|
||||
cpu_clk = clk_get(NULL, "armclk");
|
||||
if (IS_ERR(cpu_clk))
|
||||
return PTR_ERR(cpu_clk);
|
||||
|
||||
moutcore = clk_get(NULL, "moutcore");
|
||||
if (IS_ERR(moutcore))
|
||||
goto out;
|
||||
|
||||
mout_mpll = clk_get(NULL, "mout_mpll");
|
||||
if (IS_ERR(mout_mpll))
|
||||
goto out;
|
||||
|
||||
mout_apll = clk_get(NULL, "mout_apll");
|
||||
if (IS_ERR(mout_apll))
|
||||
goto out;
|
||||
|
||||
arm_regulator = regulator_get(NULL, "vdd_arm");
|
||||
if (IS_ERR(arm_regulator)) {
|
||||
printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
|
||||
goto out;
|
||||
}
|
||||
|
||||
int_regulator = regulator_get(NULL, "vdd_int");
|
||||
if (IS_ERR(int_regulator)) {
|
||||
printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check DRAM type.
|
||||
* Because DVFS level is different according to DRAM type.
|
||||
*/
|
||||
memtype = __raw_readl(S5P_VA_DMC0 + S5P_DMC0_MEMCON_OFFSET);
|
||||
memtype = (memtype >> S5P_DMC0_MEMTYPE_SHIFT);
|
||||
memtype &= S5P_DMC0_MEMTYPE_MASK;
|
||||
|
||||
if ((memtype < DDR2) && (memtype > DDR3)) {
|
||||
printk(KERN_ERR "%s: wrong memtype= 0x%x\n", __func__, memtype);
|
||||
goto out;
|
||||
} else {
|
||||
printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
|
||||
}
|
||||
|
||||
return cpufreq_register_driver(&exynos4_driver);
|
||||
|
||||
out:
|
||||
if (!IS_ERR(cpu_clk))
|
||||
clk_put(cpu_clk);
|
||||
|
||||
if (!IS_ERR(moutcore))
|
||||
clk_put(moutcore);
|
||||
|
||||
if (!IS_ERR(mout_mpll))
|
||||
clk_put(mout_mpll);
|
||||
|
||||
if (!IS_ERR(mout_apll))
|
||||
clk_put(mout_apll);
|
||||
|
||||
if (!IS_ERR(arm_regulator))
|
||||
regulator_put(arm_regulator);
|
||||
|
||||
if (!IS_ERR(int_regulator))
|
||||
regulator_put(int_regulator);
|
||||
|
||||
printk(KERN_ERR "%s: failed initialization\n", __func__);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
late_initcall(exynos4_cpufreq_init);
|
||||
484
drivers/cpufreq/s5pv210-cpufreq.c
Normal file
484
drivers/cpufreq/s5pv210-cpufreq.c
Normal file
|
|
@ -0,0 +1,484 @@
|
|||
/*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* CPU frequency scaling for S5PC110/S5PV210
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/cpufreq.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
|
||||
static struct clk *cpu_clk;
|
||||
static struct clk *dmc0_clk;
|
||||
static struct clk *dmc1_clk;
|
||||
static struct cpufreq_freqs freqs;
|
||||
|
||||
/* APLL M,P,S values for 1G/800Mhz */
|
||||
#define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1)
|
||||
#define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1)
|
||||
|
||||
/*
|
||||
* DRAM configurations to calculate refresh counter for changing
|
||||
* frequency of memory.
|
||||
*/
|
||||
struct dram_conf {
|
||||
unsigned long freq; /* HZ */
|
||||
unsigned long refresh; /* DRAM refresh counter * 1000 */
|
||||
};
|
||||
|
||||
/* DRAM configuration (DMC0 and DMC1) */
|
||||
static struct dram_conf s5pv210_dram_conf[2];
|
||||
|
||||
enum perf_level {
|
||||
L0, L1, L2, L3, L4,
|
||||
};
|
||||
|
||||
enum s5pv210_mem_type {
|
||||
LPDDR = 0x1,
|
||||
LPDDR2 = 0x2,
|
||||
DDR2 = 0x4,
|
||||
};
|
||||
|
||||
enum s5pv210_dmc_port {
|
||||
DMC0 = 0,
|
||||
DMC1,
|
||||
};
|
||||
|
||||
static struct cpufreq_frequency_table s5pv210_freq_table[] = {
|
||||
{L0, 1000*1000},
|
||||
{L1, 800*1000},
|
||||
{L2, 400*1000},
|
||||
{L3, 200*1000},
|
||||
{L4, 100*1000},
|
||||
{0, CPUFREQ_TABLE_END},
|
||||
};
|
||||
|
||||
static u32 clkdiv_val[5][11] = {
|
||||
/*
|
||||
* Clock divider value for following
|
||||
* { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
|
||||
* HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
|
||||
* ONEDRAM, MFC, G3D }
|
||||
*/
|
||||
|
||||
/* L0 : [1000/200/100][166/83][133/66][200/200] */
|
||||
{0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
|
||||
|
||||
/* L1 : [800/200/100][166/83][133/66][200/200] */
|
||||
{0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
|
||||
|
||||
/* L2 : [400/200/100][166/83][133/66][200/200] */
|
||||
{1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
|
||||
|
||||
/* L3 : [200/200/100][166/83][133/66][200/200] */
|
||||
{3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
|
||||
|
||||
/* L4 : [100/100/100][83/83][66/66][100/100] */
|
||||
{7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
|
||||
};
|
||||
|
||||
/*
|
||||
* This function set DRAM refresh counter
|
||||
* accoriding to operating frequency of DRAM
|
||||
* ch: DMC port number 0 or 1
|
||||
* freq: Operating frequency of DRAM(KHz)
|
||||
*/
|
||||
static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
|
||||
{
|
||||
unsigned long tmp, tmp1;
|
||||
void __iomem *reg = NULL;
|
||||
|
||||
if (ch == DMC0) {
|
||||
reg = (S5P_VA_DMC0 + 0x30);
|
||||
} else if (ch == DMC1) {
|
||||
reg = (S5P_VA_DMC1 + 0x30);
|
||||
} else {
|
||||
printk(KERN_ERR "Cannot find DMC port\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Find current DRAM frequency */
|
||||
tmp = s5pv210_dram_conf[ch].freq;
|
||||
|
||||
do_div(tmp, freq);
|
||||
|
||||
tmp1 = s5pv210_dram_conf[ch].refresh;
|
||||
|
||||
do_div(tmp1, tmp);
|
||||
|
||||
__raw_writel(tmp1, reg);
|
||||
}
|
||||
|
||||
int s5pv210_verify_speed(struct cpufreq_policy *policy)
|
||||
{
|
||||
if (policy->cpu)
|
||||
return -EINVAL;
|
||||
|
||||
return cpufreq_frequency_table_verify(policy, s5pv210_freq_table);
|
||||
}
|
||||
|
||||
unsigned int s5pv210_getspeed(unsigned int cpu)
|
||||
{
|
||||
if (cpu)
|
||||
return 0;
|
||||
|
||||
return clk_get_rate(cpu_clk) / 1000;
|
||||
}
|
||||
|
||||
static int s5pv210_target(struct cpufreq_policy *policy,
|
||||
unsigned int target_freq,
|
||||
unsigned int relation)
|
||||
{
|
||||
unsigned long reg;
|
||||
unsigned int index, priv_index;
|
||||
unsigned int pll_changing = 0;
|
||||
unsigned int bus_speed_changing = 0;
|
||||
|
||||
freqs.old = s5pv210_getspeed(0);
|
||||
|
||||
if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
|
||||
target_freq, relation, &index))
|
||||
return -EINVAL;
|
||||
|
||||
freqs.new = s5pv210_freq_table[index].frequency;
|
||||
freqs.cpu = 0;
|
||||
|
||||
if (freqs.new == freqs.old)
|
||||
return 0;
|
||||
|
||||
/* Finding current running level index */
|
||||
if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
|
||||
freqs.old, relation, &priv_index))
|
||||
return -EINVAL;
|
||||
|
||||
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
|
||||
|
||||
if (freqs.new > freqs.old) {
|
||||
/* Voltage up: will be implemented */
|
||||
}
|
||||
|
||||
/* Check if there need to change PLL */
|
||||
if ((index == L0) || (priv_index == L0))
|
||||
pll_changing = 1;
|
||||
|
||||
/* Check if there need to change System bus clock */
|
||||
if ((index == L4) || (priv_index == L4))
|
||||
bus_speed_changing = 1;
|
||||
|
||||
if (bus_speed_changing) {
|
||||
/*
|
||||
* Reconfigure DRAM refresh counter value for minimum
|
||||
* temporary clock while changing divider.
|
||||
* expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
|
||||
*/
|
||||
if (pll_changing)
|
||||
s5pv210_set_refresh(DMC1, 83000);
|
||||
else
|
||||
s5pv210_set_refresh(DMC1, 100000);
|
||||
|
||||
s5pv210_set_refresh(DMC0, 83000);
|
||||
}
|
||||
|
||||
/*
|
||||
* APLL should be changed in this level
|
||||
* APLL -> MPLL(for stable transition) -> APLL
|
||||
* Some clock source's clock API are not prepared.
|
||||
* Do not use clock API in below code.
|
||||
*/
|
||||
if (pll_changing) {
|
||||
/*
|
||||
* 1. Temporary Change divider for MFC and G3D
|
||||
* SCLKA2M(200/1=200)->(200/4=50)Mhz
|
||||
*/
|
||||
reg = __raw_readl(S5P_CLK_DIV2);
|
||||
reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
|
||||
reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
|
||||
(3 << S5P_CLKDIV2_MFC_SHIFT);
|
||||
__raw_writel(reg, S5P_CLK_DIV2);
|
||||
|
||||
/* For MFC, G3D dividing */
|
||||
do {
|
||||
reg = __raw_readl(S5P_CLKDIV_STAT0);
|
||||
} while (reg & ((1 << 16) | (1 << 17)));
|
||||
|
||||
/*
|
||||
* 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
|
||||
* (200/4=50)->(667/4=166)Mhz
|
||||
*/
|
||||
reg = __raw_readl(S5P_CLK_SRC2);
|
||||
reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
|
||||
reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
|
||||
(1 << S5P_CLKSRC2_MFC_SHIFT);
|
||||
__raw_writel(reg, S5P_CLK_SRC2);
|
||||
|
||||
do {
|
||||
reg = __raw_readl(S5P_CLKMUX_STAT1);
|
||||
} while (reg & ((1 << 7) | (1 << 3)));
|
||||
|
||||
/*
|
||||
* 3. DMC1 refresh count for 133Mhz if (index == L4) is
|
||||
* true refresh counter is already programed in upper
|
||||
* code. 0x287@83Mhz
|
||||
*/
|
||||
if (!bus_speed_changing)
|
||||
s5pv210_set_refresh(DMC1, 133000);
|
||||
|
||||
/* 4. SCLKAPLL -> SCLKMPLL */
|
||||
reg = __raw_readl(S5P_CLK_SRC0);
|
||||
reg &= ~(S5P_CLKSRC0_MUX200_MASK);
|
||||
reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
|
||||
__raw_writel(reg, S5P_CLK_SRC0);
|
||||
|
||||
do {
|
||||
reg = __raw_readl(S5P_CLKMUX_STAT0);
|
||||
} while (reg & (0x1 << 18));
|
||||
|
||||
}
|
||||
|
||||
/* Change divider */
|
||||
reg = __raw_readl(S5P_CLK_DIV0);
|
||||
|
||||
reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
|
||||
S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
|
||||
S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
|
||||
S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);
|
||||
|
||||
reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
|
||||
(clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
|
||||
(clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
|
||||
(clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
|
||||
(clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
|
||||
(clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
|
||||
(clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
|
||||
(clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
|
||||
|
||||
__raw_writel(reg, S5P_CLK_DIV0);
|
||||
|
||||
do {
|
||||
reg = __raw_readl(S5P_CLKDIV_STAT0);
|
||||
} while (reg & 0xff);
|
||||
|
||||
/* ARM MCS value changed */
|
||||
reg = __raw_readl(S5P_ARM_MCS_CON);
|
||||
reg &= ~0x3;
|
||||
if (index >= L3)
|
||||
reg |= 0x3;
|
||||
else
|
||||
reg |= 0x1;
|
||||
|
||||
__raw_writel(reg, S5P_ARM_MCS_CON);
|
||||
|
||||
if (pll_changing) {
|
||||
/* 5. Set Lock time = 30us*24Mhz = 0x2cf */
|
||||
__raw_writel(0x2cf, S5P_APLL_LOCK);
|
||||
|
||||
/*
|
||||
* 6. Turn on APLL
|
||||
* 6-1. Set PMS values
|
||||
* 6-2. Wait untile the PLL is locked
|
||||
*/
|
||||
if (index == L0)
|
||||
__raw_writel(APLL_VAL_1000, S5P_APLL_CON);
|
||||
else
|
||||
__raw_writel(APLL_VAL_800, S5P_APLL_CON);
|
||||
|
||||
do {
|
||||
reg = __raw_readl(S5P_APLL_CON);
|
||||
} while (!(reg & (0x1 << 29)));
|
||||
|
||||
/*
|
||||
* 7. Change souce clock from SCLKMPLL(667Mhz)
|
||||
* to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
|
||||
* (667/4=166)->(200/4=50)Mhz
|
||||
*/
|
||||
reg = __raw_readl(S5P_CLK_SRC2);
|
||||
reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
|
||||
reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
|
||||
(0 << S5P_CLKSRC2_MFC_SHIFT);
|
||||
__raw_writel(reg, S5P_CLK_SRC2);
|
||||
|
||||
do {
|
||||
reg = __raw_readl(S5P_CLKMUX_STAT1);
|
||||
} while (reg & ((1 << 7) | (1 << 3)));
|
||||
|
||||
/*
|
||||
* 8. Change divider for MFC and G3D
|
||||
* (200/4=50)->(200/1=200)Mhz
|
||||
*/
|
||||
reg = __raw_readl(S5P_CLK_DIV2);
|
||||
reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
|
||||
reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
|
||||
(clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
|
||||
__raw_writel(reg, S5P_CLK_DIV2);
|
||||
|
||||
/* For MFC, G3D dividing */
|
||||
do {
|
||||
reg = __raw_readl(S5P_CLKDIV_STAT0);
|
||||
} while (reg & ((1 << 16) | (1 << 17)));
|
||||
|
||||
/* 9. Change MPLL to APLL in MSYS_MUX */
|
||||
reg = __raw_readl(S5P_CLK_SRC0);
|
||||
reg &= ~(S5P_CLKSRC0_MUX200_MASK);
|
||||
reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
|
||||
__raw_writel(reg, S5P_CLK_SRC0);
|
||||
|
||||
do {
|
||||
reg = __raw_readl(S5P_CLKMUX_STAT0);
|
||||
} while (reg & (0x1 << 18));
|
||||
|
||||
/*
|
||||
* 10. DMC1 refresh counter
|
||||
* L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
|
||||
* Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
|
||||
*/
|
||||
if (!bus_speed_changing)
|
||||
s5pv210_set_refresh(DMC1, 200000);
|
||||
}
|
||||
|
||||
/*
|
||||
* L4 level need to change memory bus speed, hence onedram clock divier
|
||||
* and memory refresh parameter should be changed
|
||||
*/
|
||||
if (bus_speed_changing) {
|
||||
reg = __raw_readl(S5P_CLK_DIV6);
|
||||
reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
|
||||
reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
|
||||
__raw_writel(reg, S5P_CLK_DIV6);
|
||||
|
||||
do {
|
||||
reg = __raw_readl(S5P_CLKDIV_STAT1);
|
||||
} while (reg & (1 << 15));
|
||||
|
||||
/* Reconfigure DRAM refresh counter value */
|
||||
if (index != L4) {
|
||||
/*
|
||||
* DMC0 : 166Mhz
|
||||
* DMC1 : 200Mhz
|
||||
*/
|
||||
s5pv210_set_refresh(DMC0, 166000);
|
||||
s5pv210_set_refresh(DMC1, 200000);
|
||||
} else {
|
||||
/*
|
||||
* DMC0 : 83Mhz
|
||||
* DMC1 : 100Mhz
|
||||
*/
|
||||
s5pv210_set_refresh(DMC0, 83000);
|
||||
s5pv210_set_refresh(DMC1, 100000);
|
||||
}
|
||||
}
|
||||
|
||||
if (freqs.new < freqs.old) {
|
||||
/* Voltage down: will be implemented */
|
||||
}
|
||||
|
||||
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
|
||||
|
||||
printk(KERN_DEBUG "Perf changed[L%d]\n", index);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int check_mem_type(void __iomem *dmc_reg)
|
||||
{
|
||||
unsigned long val;
|
||||
|
||||
val = __raw_readl(dmc_reg + 0x4);
|
||||
val = (val & (0xf << 8));
|
||||
|
||||
return val >> 8;
|
||||
}
|
||||
|
||||
static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
|
||||
{
|
||||
unsigned long mem_type;
|
||||
|
||||
cpu_clk = clk_get(NULL, "armclk");
|
||||
if (IS_ERR(cpu_clk))
|
||||
return PTR_ERR(cpu_clk);
|
||||
|
||||
dmc0_clk = clk_get(NULL, "sclk_dmc0");
|
||||
if (IS_ERR(dmc0_clk)) {
|
||||
clk_put(cpu_clk);
|
||||
return PTR_ERR(dmc0_clk);
|
||||
}
|
||||
|
||||
dmc1_clk = clk_get(NULL, "hclk_msys");
|
||||
if (IS_ERR(dmc1_clk)) {
|
||||
clk_put(dmc0_clk);
|
||||
clk_put(cpu_clk);
|
||||
return PTR_ERR(dmc1_clk);
|
||||
}
|
||||
|
||||
if (policy->cpu != 0)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* check_mem_type : This driver only support LPDDR & LPDDR2.
|
||||
* other memory type is not supported.
|
||||
*/
|
||||
mem_type = check_mem_type(S5P_VA_DMC0);
|
||||
|
||||
if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
|
||||
printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Find current refresh counter and frequency each DMC */
|
||||
s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
|
||||
s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
|
||||
|
||||
s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
|
||||
s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
|
||||
|
||||
policy->cur = policy->min = policy->max = s5pv210_getspeed(0);
|
||||
|
||||
cpufreq_frequency_table_get_attr(s5pv210_freq_table, policy->cpu);
|
||||
|
||||
policy->cpuinfo.transition_latency = 40000;
|
||||
|
||||
return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table);
|
||||
}
|
||||
|
||||
static struct cpufreq_driver s5pv210_driver = {
|
||||
.flags = CPUFREQ_STICKY,
|
||||
.verify = s5pv210_verify_speed,
|
||||
.target = s5pv210_target,
|
||||
.get = s5pv210_getspeed,
|
||||
.init = s5pv210_cpu_init,
|
||||
.name = "s5pv210",
|
||||
#ifdef CONFIG_PM
|
||||
.suspend = s5pv210_cpufreq_suspend,
|
||||
.resume = s5pv210_cpufreq_resume,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int __init s5pv210_cpufreq_init(void)
|
||||
{
|
||||
return cpufreq_register_driver(&s5pv210_driver);
|
||||
}
|
||||
|
||||
late_initcall(s5pv210_cpufreq_init);
|
||||
Loading…
Reference in a new issue