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msm: pcie: support controller PHY settings for Gen3 and Gen4

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There are PCIe Gen3 and Gen4 PHY related settings which has to be
programmed at the PCIe controller. Add the infrastructure to
support such settings. Settings for Gen3 also needs to be
applied to Gen4 controllers. Move existing settings to the
new infrastructure.

Change-Id: I67c7c3d7c5bfa13ed30c8fca55f941c8cab0a7f0
Signed-off-by: Tony Truong <truong@codeaurora.org>
This commit is contained in:
Tony Truong 2020-11-05 12:47:25 -08:00 • committed by Gerrit - the friendly Code Review server
commit f83ec092e8
1 changed files with 31 additions and 9 deletions
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40
drivers/pci/controller/pci-msm.c
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@ -45,6 +45,10 @@
#define PCIE_GEN3_SPCIE_CAP (0x0154)
#define PCIE_GEN3_GEN2_CTRL (0x080c)
#define PCIE_GEN3_RELATED (0x0890)
#define PCIE_GEN3_RELATED_RATE_SHADOW_SEL_MASK (BIT(25) | BIT(24))
/* 0 - Gen3, 1 - Gen4 */
#define PCIE_GEN3_RELATED_RATE_SHADOW_SEL(x) ((x) - PCI_EXP_LNKCAP_SLS_8_0GB)
#define PCIE_GEN3_EQ_CONTROL (0x08a8)
#define PCIE_GEN3_EQ_PSET_REQ_VEC_MASK (GENMASK(23, 8))
@ -3266,6 +3270,31 @@ static void msm_pcie_config_core_preset(struct msm_pcie_dev_t *pcie_dev)
0);
}
/* Controller settings related to PCIe PHY */
static void msm_pcie_config_controller_phy(struct msm_pcie_dev_t *pcie_dev)
{
int i;
u32 supported_link_speed =
readl_relaxed(pcie_dev->dm_core + PCIE20_CAP + PCI_EXP_LNKCAP) &
PCI_EXP_LNKCAP_SLS;
/* settings apply to GEN3 and above */
for (i = PCI_EXP_LNKCAP_SLS_8_0GB; i <= supported_link_speed; i++) {
/* select which GEN speed to configure settings for */
msm_pcie_write_reg_field(pcie_dev->dm_core, PCIE_GEN3_RELATED,
PCIE_GEN3_RELATED_RATE_SHADOW_SEL_MASK,
PCIE_GEN3_RELATED_RATE_SHADOW_SEL(i));
msm_pcie_write_reg_field(pcie_dev->dm_core, PCIE_GEN3_EQ_CONTROL,
PCIE_GEN3_EQ_PSET_REQ_VEC_MASK,
pcie_dev->eq_pset_req_vec);
/* GEN3_ZRXDC_NONCOMPL */
msm_pcie_write_mask(pcie_dev->dm_core +
PCIE_GEN3_RELATED, BIT(0), 0);
}
}
static void msm_pcie_config_controller(struct msm_pcie_dev_t *dev)
{
PCIE_DBG(dev, "RC%d\n", dev->rc_idx);
@ -3829,15 +3858,8 @@ static int msm_pcie_link_train(struct msm_pcie_dev_t *dev)
msm_pcie_write_reg_field(dev->dm_core,
PCIE_GEN3_GEN2_CTRL, 0x1f00, 1);
msm_pcie_write_mask(dev->dm_core,
PCIE_GEN3_EQ_CONTROL, 0x20);
msm_pcie_write_reg_field(dev->dm_core, PCIE_GEN3_EQ_CONTROL,
PCIE_GEN3_EQ_PSET_REQ_VEC_MASK,
dev->eq_pset_req_vec);
msm_pcie_write_mask(dev->dm_core +
PCIE_GEN3_RELATED, BIT(0), 0);
/* Controller settings related to PCIe PHY */
msm_pcie_config_controller_phy(dev);
/* configure PCIe preset */
msm_pcie_config_core_preset(dev);