mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 02:32:09 -04:00
Tegra clock fixes for 3.20
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUz5H9AAoJEFFb18rurjwTwssP/1luchJTB3qo+tqAIYYADgA4 9QLQqfgIqZuJzzCNYgauELwN5M8S02ZABRzY9OOHnUY6BvoHPMpcOEey7i33ZYTJ 9l4TFBOQyZE6W8tcyVL47pc9cjZydz9KKMO+/T5M16YyYoNZ1rXeGUli5j5sl2j7 KoNurjC6C9Hw0M8+6CBTk4tYcMtxXeIacSGhV4VM03qKWj3e7485z0tYTG9yKfVD ol3KKGwjg1eZ9FSavMVYYnWajXZ7zlbB1PFqWO6V9h7DKmJMINbXGf/qr+/8eYSq zefWEYs1uGKunFtDv3C8wGRnl8ronBHehS2/xPpVEni0Eu2kJo1v8wDmftZ5ZyFW 86ZdS4JTWD1/A2buEbJ3Ct30reNasGFUGNxIrYROglY4dK6DEPCMEFx5ZNiOhxlJ +BMjcsDzTt1gUWHbpxHrIZFErtHKcxtHeVckcZJgh87bnHVQKTAJ3cL9OJSWatqO lBDIsFxSOLap4gMKcMNddOEI8JNL1VZh+I/GdTh6VE2rhcurMNHvxmWL1TJ94/w8 tRHRU5kRdYmxPzL98nDSR0h8WXShdWmnYNr+m2fk8iiPsI4umh/RS014kPVUYKq9 a16cHkq88x3mKlEcyARG9tJK9oOCC5MuNuMPsPKf1dETOgHbAixlJVK5FHzHLjNr fERakm8nBM3rMSlgBbUL =k023 -----END PGP SIGNATURE----- Merge tag 'tegra-clk-3.20' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-next Tegra clock fixes for 3.20
This commit is contained in:
Michael Turquette
commit
f85c6edfae
12 changed files with 532 additions and 396 deletions
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@ -15,3 +15,4 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
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obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
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obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o
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obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o
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@ -64,10 +64,8 @@ enum clk_id {
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tegra_clk_disp2,
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tegra_clk_dp2,
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tegra_clk_dpaux,
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tegra_clk_dsia,
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tegra_clk_dsialp,
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tegra_clk_dsia_mux,
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tegra_clk_dsib,
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tegra_clk_dsiblp,
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tegra_clk_dsib_mux,
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tegra_clk_dtv,
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@ -816,7 +816,9 @@ const struct clk_ops tegra_clk_plle_ops = {
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.enable = clk_plle_enable,
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};
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#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
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#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
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defined(CONFIG_ARCH_TEGRA_124_SOC) || \
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defined(CONFIG_ARCH_TEGRA_132_SOC)
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static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
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unsigned long parent_rate)
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@ -1505,7 +1507,9 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
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return clk;
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}
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#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
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#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
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defined(CONFIG_ARCH_TEGRA_124_SOC) || \
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defined(CONFIG_ARCH_TEGRA_132_SOC)
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static const struct clk_ops tegra_clk_pllxc_ops = {
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.is_enabled = clk_pll_is_enabled,
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.enable = clk_pll_iddq_enable,
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@ -1565,7 +1569,7 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
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parent = __clk_lookup(parent_name);
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if (!parent) {
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WARN(1, "parent clk %s of %s must be registered first\n",
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name, parent_name);
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parent_name, name);
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return ERR_PTR(-EINVAL);
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}
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@ -1665,7 +1669,7 @@ struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
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parent = __clk_lookup(parent_name);
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if (!parent) {
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WARN(1, "parent clk %s of %s must be registered first\n",
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name, parent_name);
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parent_name, name);
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return ERR_PTR(-EINVAL);
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}
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@ -1706,7 +1710,7 @@ struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
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parent = __clk_lookup(parent_name);
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if (!parent) {
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WARN(1, "parent clk %s of %s must be registered first\n",
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name, parent_name);
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parent_name, name);
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return ERR_PTR(-EINVAL);
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}
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@ -1802,7 +1806,7 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
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}
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#endif
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#ifdef CONFIG_ARCH_TEGRA_124_SOC
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#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
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static const struct clk_ops tegra_clk_pllss_ops = {
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.is_enabled = clk_pll_is_enabled,
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.enable = clk_pll_iddq_enable,
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@ -1830,7 +1834,7 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
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parent = __clk_lookup(parent_name);
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if (!parent) {
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WARN(1, "parent clk %s of %s must be registered first\n",
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name, parent_name);
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parent_name, name);
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return ERR_PTR(-EINVAL);
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}
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@ -434,10 +434,10 @@ static struct tegra_periph_init_data periph_clks[] = {
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MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda),
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MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x),
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MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir),
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MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, tegra_clk_sdmmc1),
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MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, tegra_clk_sdmmc2),
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MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, tegra_clk_sdmmc3),
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MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, 0, tegra_clk_sdmmc4),
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MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1),
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MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2),
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MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3),
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MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4),
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MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
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MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
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MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
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@ -470,10 +470,10 @@ static struct tegra_periph_init_data periph_clks[] = {
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MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1),
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MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1),
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MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),
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MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, tegra_clk_sdmmc1_8),
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MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, tegra_clk_sdmmc2_8),
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MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, tegra_clk_sdmmc3_8),
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MUX8("sdmmc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC4, 15, 0, tegra_clk_sdmmc4_8),
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MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_8),
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MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_8),
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MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_8),
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MUX8("sdmmc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_8),
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MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8),
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MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8),
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MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8),
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@ -537,8 +537,6 @@ static struct tegra_periph_init_data gate_clks[] = {
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GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),
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GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),
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GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
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GATE("dsia", "dsia_mux", 48, 0, tegra_clk_dsia, 0),
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GATE("dsib", "dsib_mux", 82, 0, tegra_clk_dsib, 0),
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GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED),
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GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
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GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0),
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@ -715,7 +715,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
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[tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
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[tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
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[tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
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[tegra_clk_dsia] = { .dt_id = TEGRA114_CLK_DSIA, .present = true },
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[tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
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[tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
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[tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
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@ -739,7 +738,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
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[tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
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[tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
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[tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
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[tegra_clk_dsib] = { .dt_id = TEGRA114_CLK_DSIB, .present = true },
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[tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
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[tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
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[tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
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@ -1224,6 +1222,14 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
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clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
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clks[TEGRA114_CLK_DSIB_MUX] = clk;
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clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
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0, 48, periph_clk_enb_refcnt);
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clks[TEGRA114_CLK_DSIA] = clk;
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clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
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0, 82, periph_clk_enb_refcnt);
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clks[TEGRA114_CLK_DSIB] = clk;
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/* emc mux */
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clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
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ARRAY_SIZE(mux_pllmcp_clkm),
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -28,6 +28,14 @@
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#include "clk.h"
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#include "clk-id.h"
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/*
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* TEGRA124_CAR_BANK_COUNT: the number of peripheral clock register
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* banks present in the Tegra124/132 CAR IP block. The banks are
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* identified by single letters, e.g.: L, H, U, V, W, X. See
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* periph_regs[] in drivers/clk/tegra/clk.c
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*/
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#define TEGRA124_CAR_BANK_COUNT 6
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#define CLK_SOURCE_CSITE 0x1d4
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#define CLK_SOURCE_EMC 0x19c
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@ -128,7 +136,6 @@ static unsigned long osc_freq;
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static unsigned long pll_ref_freq;
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static DEFINE_SPINLOCK(pll_d_lock);
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static DEFINE_SPINLOCK(pll_d2_lock);
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static DEFINE_SPINLOCK(pll_e_lock);
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static DEFINE_SPINLOCK(pll_re_lock);
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static DEFINE_SPINLOCK(pll_u_lock);
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@ -145,11 +152,6 @@ static unsigned long tegra124_input_freq[] = {
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[12] = 260000000,
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};
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static const char *mux_plld_out0_plld2_out0[] = {
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"pll_d_out0", "pll_d2_out0",
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};
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#define mux_plld_out0_plld2_out0_idx NULL
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static const char *mux_pllmcp_clkm[] = {
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"pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
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};
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@ -783,7 +785,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
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[tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true },
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[tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true },
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[tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true },
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[tegra_clk_dsia] = { .dt_id = TEGRA124_CLK_DSIA, .present = true },
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[tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true },
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[tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true },
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[tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true },
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@ -809,7 +810,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
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[tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
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[tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
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[tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
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[tegra_clk_dsib] = { .dt_id = TEGRA124_CLK_DSIB, .present = true },
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[tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
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[tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true },
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[tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true },
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@ -949,8 +949,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
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[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
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[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
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[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
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[tegra_clk_dsia_mux] = { .dt_id = TEGRA124_CLK_DSIA_MUX, .present = true },
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[tegra_clk_dsib_mux] = { .dt_id = TEGRA124_CLK_DSIB_MUX, .present = true },
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};
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static struct tegra_devclk devclks[] __initdata = {
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@ -1112,17 +1110,17 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base,
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1, 2);
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clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
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/* dsia mux */
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clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
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ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
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clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
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clks[TEGRA124_CLK_DSIA_MUX] = clk;
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clk = clk_register_gate(NULL, "plld_dsi", "plld_out0", 0,
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clk_base + PLLD_MISC, 30, 0, &pll_d_lock);
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clks[TEGRA124_CLK_PLLD_DSI] = clk;
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/* dsib mux */
|
||||
clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
|
||||
ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
|
||||
clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
|
||||
clks[TEGRA124_CLK_DSIB_MUX] = clk;
|
||||
clk = tegra_clk_register_periph_gate("dsia", "plld_dsi", 0, clk_base,
|
||||
0, 48, periph_clk_enb_refcnt);
|
||||
clks[TEGRA124_CLK_DSIA] = clk;
|
||||
|
||||
clk = tegra_clk_register_periph_gate("dsib", "plld_dsi", 0, clk_base,
|
||||
0, 82, periph_clk_enb_refcnt);
|
||||
clks[TEGRA124_CLK_DSIB] = clk;
|
||||
|
||||
/* emc mux */
|
||||
clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
|
||||
|
|
@ -1351,7 +1349,7 @@ static const struct of_device_id pmc_match[] __initconst = {
|
|||
{},
|
||||
};
|
||||
|
||||
static struct tegra_clk_init_table init_table[] __initdata = {
|
||||
static struct tegra_clk_init_table common_init_table[] __initdata = {
|
||||
{TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0},
|
||||
|
|
@ -1368,6 +1366,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
|||
{TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0},
|
||||
{TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1},
|
||||
{TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0},
|
||||
{TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0},
|
||||
{TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1},
|
||||
{TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1},
|
||||
{TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1},
|
||||
|
|
@ -1385,27 +1385,73 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
|||
{TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0},
|
||||
{TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0},
|
||||
{TEGRA124_CLK_EMC, TEGRA124_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0},
|
||||
{TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0},
|
||||
/* This MUST be the last entry. */
|
||||
{TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
|
||||
};
|
||||
|
||||
static struct tegra_clk_init_table tegra124_init_table[] __initdata = {
|
||||
{TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0},
|
||||
{TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1},
|
||||
/* This MUST be the last entry. */
|
||||
{TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
|
||||
};
|
||||
|
||||
/* Tegra132 requires the SOC_THERM clock to remain active */
|
||||
static struct tegra_clk_init_table tegra132_init_table[] __initdata = {
|
||||
{TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1},
|
||||
/* This MUST be the last entry. */
|
||||
{TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
|
||||
};
|
||||
|
||||
/**
|
||||
* tegra124_clock_apply_init_table - initialize clocks on Tegra124 SoCs
|
||||
*
|
||||
* Program an initial clock rate and enable or disable clocks needed
|
||||
* by the rest of the kernel, for Tegra124 SoCs. It is intended to be
|
||||
* called by assigning a pointer to it to tegra_clk_apply_init_table -
|
||||
* this will be called as an arch_initcall. No return value.
|
||||
*/
|
||||
static void __init tegra124_clock_apply_init_table(void)
|
||||
{
|
||||
tegra_init_from_table(init_table, clks, TEGRA124_CLK_CLK_MAX);
|
||||
tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
|
||||
tegra_init_from_table(tegra124_init_table, clks, TEGRA124_CLK_CLK_MAX);
|
||||
}
|
||||
|
||||
static void __init tegra124_clock_init(struct device_node *np)
|
||||
/**
|
||||
* tegra132_clock_apply_init_table - initialize clocks on Tegra132 SoCs
|
||||
*
|
||||
* Program an initial clock rate and enable or disable clocks needed
|
||||
* by the rest of the kernel, for Tegra132 SoCs. It is intended to be
|
||||
* called by assigning a pointer to it to tegra_clk_apply_init_table -
|
||||
* this will be called as an arch_initcall. No return value.
|
||||
*/
|
||||
static void __init tegra132_clock_apply_init_table(void)
|
||||
{
|
||||
tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
|
||||
tegra_init_from_table(tegra132_init_table, clks, TEGRA124_CLK_CLK_MAX);
|
||||
}
|
||||
|
||||
/**
|
||||
* tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
|
||||
* @np: struct device_node * of the DT node for the SoC CAR IP block
|
||||
*
|
||||
* Register most of the clocks controlled by the CAR IP block, along
|
||||
* with a few clocks controlled by the PMC IP block. Everything in
|
||||
* this function should be common to Tegra124 and Tegra132. XXX The
|
||||
* PMC clock initialization should probably be moved to PMC-specific
|
||||
* driver code. No return value.
|
||||
*/
|
||||
static void __init tegra124_132_clock_init_pre(struct device_node *np)
|
||||
{
|
||||
struct device_node *node;
|
||||
u32 plld_base;
|
||||
|
||||
clk_base = of_iomap(np, 0);
|
||||
if (!clk_base) {
|
||||
pr_err("ioremap tegra124 CAR failed\n");
|
||||
pr_err("ioremap tegra124/tegra132 CAR failed\n");
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -1423,7 +1469,8 @@ static void __init tegra124_clock_init(struct device_node *np)
|
|||
return;
|
||||
}
|
||||
|
||||
clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, 6);
|
||||
clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX,
|
||||
TEGRA124_CAR_BANK_COUNT);
|
||||
if (!clks)
|
||||
return;
|
||||
|
||||
|
|
@ -1437,13 +1484,76 @@ static void __init tegra124_clock_init(struct device_node *np)
|
|||
tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params);
|
||||
tegra_pmc_clk_init(pmc_base, tegra124_clks);
|
||||
|
||||
/* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
|
||||
plld_base = clk_readl(clk_base + PLLD_BASE);
|
||||
plld_base &= ~BIT(25);
|
||||
clk_writel(plld_base, clk_base + PLLD_BASE);
|
||||
}
|
||||
|
||||
/**
|
||||
* tegra124_132_clock_init_post - clock initialization postamble for T124/T132
|
||||
* @np: struct device_node * of the DT node for the SoC CAR IP block
|
||||
*
|
||||
* Register most of the along with a few clocks controlled by the PMC
|
||||
* IP block. Everything in this function should be common to Tegra124
|
||||
* and Tegra132. This function must be called after
|
||||
* tegra124_132_clock_init_pre(), otherwise clk_base and pmc_base will
|
||||
* not be set. No return value.
|
||||
*/
|
||||
static void __init tegra124_132_clock_init_post(struct device_node *np)
|
||||
{
|
||||
tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,
|
||||
&pll_x_params);
|
||||
&pll_x_params);
|
||||
tegra_add_of_provider(np);
|
||||
tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
|
||||
|
||||
tegra_clk_apply_init_table = tegra124_clock_apply_init_table;
|
||||
|
||||
tegra_cpu_car_ops = &tegra124_cpu_car_ops;
|
||||
}
|
||||
|
||||
/**
|
||||
* tegra124_clock_init - Tegra124-specific clock initialization
|
||||
* @np: struct device_node * of the DT node for the SoC CAR IP block
|
||||
*
|
||||
* Register most SoC clocks for the Tegra124 system-on-chip. Most of
|
||||
* this code is shared between the Tegra124 and Tegra132 SoCs,
|
||||
* although some of the initial clock settings and CPU clocks differ.
|
||||
* Intended to be called by the OF init code when a DT node with the
|
||||
* "nvidia,tegra124-car" string is encountered, and declared with
|
||||
* CLK_OF_DECLARE. No return value.
|
||||
*/
|
||||
static void __init tegra124_clock_init(struct device_node *np)
|
||||
{
|
||||
tegra124_132_clock_init_pre(np);
|
||||
tegra_clk_apply_init_table = tegra124_clock_apply_init_table;
|
||||
tegra124_132_clock_init_post(np);
|
||||
}
|
||||
|
||||
/**
|
||||
* tegra132_clock_init - Tegra132-specific clock initialization
|
||||
* @np: struct device_node * of the DT node for the SoC CAR IP block
|
||||
*
|
||||
* Register most SoC clocks for the Tegra132 system-on-chip. Most of
|
||||
* this code is shared between the Tegra124 and Tegra132 SoCs,
|
||||
* although some of the initial clock settings and CPU clocks differ.
|
||||
* Intended to be called by the OF init code when a DT node with the
|
||||
* "nvidia,tegra132-car" string is encountered, and declared with
|
||||
* CLK_OF_DECLARE. No return value.
|
||||
*/
|
||||
static void __init tegra132_clock_init(struct device_node *np)
|
||||
{
|
||||
tegra124_132_clock_init_pre(np);
|
||||
|
||||
/*
|
||||
* On Tegra132, these clocks are controlled by the
|
||||
* CLUSTER_clocks IP block, located in the CPU complex
|
||||
*/
|
||||
tegra124_clks[tegra_clk_cclk_g].present = false;
|
||||
tegra124_clks[tegra_clk_cclk_lp].present = false;
|
||||
tegra124_clks[tegra_clk_pll_x].present = false;
|
||||
tegra124_clks[tegra_clk_pll_x_out0].present = false;
|
||||
|
||||
tegra_clk_apply_init_table = tegra132_clock_apply_init_table;
|
||||
tegra124_132_clock_init_post(np);
|
||||
}
|
||||
CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);
|
||||
CLK_OF_DECLARE(tegra132, "nvidia,tegra132-car", tegra132_clock_init);
|
||||
|
|
|
|||
|
|
@ -302,10 +302,13 @@ struct clk ** __init tegra_lookup_dt_id(int clk_id,
|
|||
|
||||
tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
|
||||
|
||||
void __init tegra_clocks_apply_init_table(void)
|
||||
static int __init tegra_clocks_apply_init_table(void)
|
||||
{
|
||||
if (!tegra_clk_apply_init_table)
|
||||
return;
|
||||
return 0;
|
||||
|
||||
tegra_clk_apply_init_table();
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(tegra_clocks_apply_init_table);
|
||||
|
|
|
|||
Loading…
Reference in a new issue