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iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126

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Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq
lines for gerror, eventq and cmdq-sync.

New named irq "combined" is set as a errata workaround, which allows to
share the irq line by register single irq handler for all the interrupts.

Acked-by: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Geetha sowjanya <[email protected]>
[will: reworked irq equality checking and added SPI check]
Signed-off-by: Will Deacon <[email protected]>
This commit is contained in:
Geetha Sowjanya 2017-06-23 19:04:36 +05:30 • committed by Will Deacon
commit f935448acf
4 changed files with 121 additions and 43 deletions
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1
Documentation/arm64/silicon-errata.txt
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@ -63,6 +63,7 @@ stable kernels.
| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
| Cavium | ThunderX SMMUv2 | #27704 | N/A |
| Cavium | ThunderX2 SMMUv3| #74 | N/A |
| Cavium | ThunderX2 SMMUv3| #126 | N/A |
| | | | |
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
| | | | |