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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-11 15:11:48 -04:00
qcacmn: Adding hal support for ipq5018
Added new qca5018 hal folder to add ipq5018 specific changes. This includes interface files to access ipq5018 hal registers. Change-Id: I7e19dc7c8719fa175695b268dc904fb4521a3330
This commit is contained in:
Basamma Yakkanahalli
nshrivas
parent
65f217ba99
commit
f9529fbba8
4 changed files with 2705 additions and 0 deletions
1894
hal/wifi3.0/qca5018/hal_5018.c
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1894
hal/wifi3.0/qca5018/hal_5018.c
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File diff suppressed because it is too large
Load diff
366
hal/wifi3.0/qca5018/hal_5018_rx.h
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366
hal/wifi3.0/qca5018/hal_5018_rx.h
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/*
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* Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
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((uint8_t *)(link_desc_va) + \
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RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET)
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#define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \
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((uint8_t *)(msdu0) + \
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RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)
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#define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \
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((uint8_t *)(ent_ring_desc) + \
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RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET)
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#define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \
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((uint8_t *)(dst_ring_desc) + \
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REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET)
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#define HAL_RX_GET_FC_VALID(rx_mpdu_start) \
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HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MPDU_FRAME_CONTROL_VALID)
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#define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \
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HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, TO_DS)
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#define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \
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HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD1_VALID)
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#define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \
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HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD2_VALID)
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#define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \
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HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, RXPCU_MPDU_FILTER_IN_CATEGORY)
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#define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \
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HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, PHY_PPDU_ID)
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#define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \
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HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, SW_FRAME_GROUP_ID)
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#define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \
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do { \
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reg_val &= \
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~(HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_BMSK |\
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HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \
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HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \
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reg_val |= \
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HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
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SOFT_REORDER_DEST_RING, \
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(reo_params)->frag_dst_ring) | \
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HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
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AGING_LIST_ENABLE, 1) |\
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HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
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AGING_FLUSH_ENABLE, 1);\
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HAL_REG_WRITE((soc), \
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HWIO_REO_R0_GENERAL_ENABLE_ADDR( \
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SEQ_WCSS_UMAC_REO_REG_OFFSET), \
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(reg_val)); \
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} while (0)
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#define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
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((struct rx_msdu_desc_info *) \
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_OFFSET_TO_BYTE_PTR((msdu_details_ptr), \
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UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET))
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#define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \
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((struct rx_msdu_details *) \
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_OFFSET_TO_BYTE_PTR((link_desc),\
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UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET))
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#define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \
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(_HAL_MS( \
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(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
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msdu_end_tlv.rx_msdu_end), \
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RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET)), \
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RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK, \
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RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB))
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#define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_10_FIRST_MSDU_OFFSET)), \
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RX_MSDU_END_10_FIRST_MSDU_MASK, \
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RX_MSDU_END_10_FIRST_MSDU_LSB))
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#define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_10_LAST_MSDU_OFFSET)), \
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RX_MSDU_END_10_LAST_MSDU_MASK, \
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RX_MSDU_END_10_LAST_MSDU_LSB))
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#define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_10_SA_IS_VALID_OFFSET)), \
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RX_MSDU_END_10_SA_IS_VALID_MASK, \
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RX_MSDU_END_10_SA_IS_VALID_LSB))
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#define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_10_DA_IS_VALID_OFFSET)), \
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RX_MSDU_END_10_DA_IS_VALID_MASK, \
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RX_MSDU_END_10_DA_IS_VALID_LSB))
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#define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_10_DA_IS_MCBC_OFFSET)), \
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RX_MSDU_END_10_DA_IS_MCBC_MASK, \
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RX_MSDU_END_10_DA_IS_MCBC_LSB))
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#define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET)), \
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RX_MSDU_END_10_L3_HEADER_PADDING_MASK, \
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RX_MSDU_END_10_L3_HEADER_PADDING_LSB))
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#define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_11_SA_IDX_OFFSET)), \
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RX_MSDU_END_11_SA_IDX_MASK, \
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RX_MSDU_END_11_SA_IDX_LSB))
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#define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET)), \
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RX_MSDU_END_14_SA_SW_PEER_ID_MASK, \
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RX_MSDU_END_14_SA_SW_PEER_ID_LSB))
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#define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_14_CCE_METADATA_OFFSET)), \
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RX_MSDU_END_14_CCE_METADATA_MASK, \
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RX_MSDU_END_14_CCE_METADATA_LSB))
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#define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET)), \
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RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK, \
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RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB))
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#define HAL_RX_MPDU_SW_FRAME_GROUP_ID_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
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RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), \
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RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, \
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RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)) \
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#define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
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RX_MPDU_INFO_10_SW_PEER_ID_OFFSET)), \
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RX_MPDU_INFO_10_SW_PEER_ID_MASK, \
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RX_MPDU_INFO_10_SW_PEER_ID_LSB))
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#define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET)), \
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RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK, \
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RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB))
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#define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET)), \
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RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK, \
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RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB))
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#define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \
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RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \
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RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB))
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#define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \
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RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \
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RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB))
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#define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET)), \
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RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK, \
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RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB))
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#define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \
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RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \
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RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB))
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#define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \
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RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \
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RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB))
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#define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET)), \
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RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK, \
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RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB))
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#define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \
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RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \
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RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB))
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#define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \
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RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \
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RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB))
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#define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \
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RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK, \
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RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB))
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#define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \
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RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \
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RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB))
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#define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \
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RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \
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RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB))
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#define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \
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RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK, \
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RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB))
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#define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
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RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \
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RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK, \
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RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB))
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#define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \
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RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK, \
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RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB))
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#define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_FR_DS_OFFSET)), \
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RX_MPDU_INFO_11_FR_DS_MASK, \
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RX_MPDU_INFO_11_FR_DS_LSB))
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#define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_TO_DS_OFFSET)), \
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RX_MPDU_INFO_11_TO_DS_MASK, \
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RX_MPDU_INFO_11_TO_DS_LSB))
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#define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET)), \
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RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK, \
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RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB))
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#define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_3_PN_31_0_OFFSET)), \
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RX_MPDU_INFO_3_PN_31_0_MASK, \
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RX_MPDU_INFO_3_PN_31_0_LSB))
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#define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_4_PN_63_32_OFFSET)), \
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RX_MPDU_INFO_4_PN_63_32_MASK, \
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RX_MPDU_INFO_4_PN_63_32_LSB))
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#define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_5_PN_95_64_OFFSET)), \
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RX_MPDU_INFO_5_PN_95_64_MASK, \
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RX_MPDU_INFO_5_PN_95_64_LSB))
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#define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_6_PN_127_96_OFFSET)), \
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RX_MPDU_INFO_6_PN_127_96_MASK, \
|
||||
RX_MPDU_INFO_6_PN_127_96_LSB))
|
||||
|
||||
#define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \
|
||||
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
|
||||
RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET)), \
|
||||
RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK, \
|
||||
RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB))
|
||||
|
||||
#define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \
|
||||
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
|
||||
RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET)), \
|
||||
RX_MSDU_END_10_FLOW_IDX_INVALID_MASK, \
|
||||
RX_MSDU_END_10_FLOW_IDX_INVALID_LSB))
|
||||
|
||||
#define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \
|
||||
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
|
||||
RX_MSDU_END_12_FLOW_IDX_OFFSET)), \
|
||||
RX_MSDU_END_12_FLOW_IDX_MASK, \
|
||||
RX_MSDU_END_12_FLOW_IDX_LSB))
|
||||
|
||||
#define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \
|
||||
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
|
||||
RX_MSDU_END_13_FSE_METADATA_OFFSET)), \
|
||||
RX_MSDU_END_13_FSE_METADATA_MASK, \
|
||||
RX_MSDU_END_13_FSE_METADATA_LSB))
|
||||
|
||||
#define HAL_RX_MPDU_GET_PHY_PPDU_ID(_rx_mpdu_info) \
|
||||
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
|
||||
RX_MPDU_INFO_9_PHY_PPDU_ID_OFFSET)), \
|
||||
RX_MPDU_INFO_9_PHY_PPDU_ID_MASK, \
|
||||
RX_MPDU_INFO_9_PHY_PPDU_ID_LSB)) \
|
||||
|
||||
#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
|
||||
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
|
||||
RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \
|
||||
RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \
|
||||
RX_MSDU_START_5_MIMO_SS_BITMAP_LSB))
|
||||
|
||||
#ifdef GET_MSDU_AGGREGATION
|
||||
#define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\
|
||||
{\
|
||||
struct rx_msdu_end *rx_msdu_end;\
|
||||
bool first_msdu, last_msdu; \
|
||||
rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\
|
||||
first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_10, FIRST_MSDU);\
|
||||
last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_10, LAST_MSDU);\
|
||||
if (first_msdu && last_msdu)\
|
||||
rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\
|
||||
else\
|
||||
rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \
|
||||
} \
|
||||
|
||||
#else
|
||||
#define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)
|
||||
#endif
|
||||
|
||||
#define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \
|
||||
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
|
||||
RX_MPDU_INFO_7_TID_OFFSET)), \
|
||||
RX_MPDU_INFO_7_TID_MASK, \
|
||||
RX_MPDU_INFO_7_TID_LSB))
|
||||
|
||||
#define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \
|
||||
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \
|
||||
RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \
|
||||
RX_MSDU_START_5_RECEPTION_TYPE_MASK, \
|
||||
RX_MSDU_START_5_RECEPTION_TYPE_LSB))
|
||||
209
hal/wifi3.0/qca5018/hal_5018_tx.h
Normal file
209
hal/wifi3.0/qca5018/hal_5018_tx.h
Normal file
|
|
@ -0,0 +1,209 @@
|
|||
/*
|
||||
* Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
#include "hal_hw_headers.h"
|
||||
#include "hal_internal.h"
|
||||
#include "cdp_txrx_mon_struct.h"
|
||||
#include "qdf_trace.h"
|
||||
#include "hal_rx.h"
|
||||
#include "hal_tx.h"
|
||||
#include "dp_types.h"
|
||||
#include "hal_api_mon.h"
|
||||
|
||||
/**
|
||||
* hal_tx_desc_set_dscp_tid_table_id_5018() - Sets DSCP to TID conversion
|
||||
* table ID
|
||||
* @desc: Handle to Tx Descriptor
|
||||
* @id: DSCP to tid conversion table to be used for this frame
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
static void hal_tx_desc_set_dscp_tid_table_id_5018(void *desc, uint8_t id)
|
||||
{
|
||||
HAL_SET_FLD(desc, TCL_DATA_CMD_5,
|
||||
DSCP_TID_TABLE_NUM) |=
|
||||
HAL_TX_SM(TCL_DATA_CMD_5, DSCP_TID_TABLE_NUM, id);
|
||||
}
|
||||
|
||||
#define DSCP_TID_TABLE_SIZE 24
|
||||
#define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
|
||||
#define HAL_TX_NUM_DSCP_REGISTER_SIZE 32
|
||||
|
||||
/**
|
||||
* hal_tx_set_dscp_tid_map_5018() - Configure default DSCP to TID map table
|
||||
* @soc: HAL SoC context
|
||||
* @map: DSCP-TID mapping table
|
||||
* @id: mapping table ID - 0,1
|
||||
*
|
||||
* DSCP are mapped to 8 TID values using TID values programmed
|
||||
* in two set of mapping registers DSCP_TID1_MAP_<0 to 6> (id = 0)
|
||||
* and DSCP_TID2_MAP_<0 to 6> (id = 1)
|
||||
* Each mapping register has TID mapping for 10 DSCP values
|
||||
*
|
||||
* Return: none
|
||||
*/
|
||||
static void hal_tx_set_dscp_tid_map_5018(struct hal_soc *soc,
|
||||
uint8_t *map, uint8_t id)
|
||||
{
|
||||
int i;
|
||||
uint32_t addr, cmn_reg_addr;
|
||||
uint32_t value = 0, regval;
|
||||
uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
|
||||
|
||||
if (id >= HAL_MAX_HW_DSCP_TID_V2_MAPS)
|
||||
return;
|
||||
|
||||
cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
|
||||
SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
|
||||
|
||||
addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
|
||||
SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET,
|
||||
id * NUM_WORDS_PER_DSCP_TID_TABLE);
|
||||
|
||||
/* Enable read/write access */
|
||||
regval = HAL_REG_READ(soc, cmn_reg_addr);
|
||||
regval |=
|
||||
(1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
|
||||
|
||||
HAL_REG_WRITE(soc, cmn_reg_addr, regval);
|
||||
|
||||
/* Write 8 (24 bits) DSCP-TID mappings in each interation */
|
||||
for (i = 0; i < 64; i += 8) {
|
||||
value = (map[i] |
|
||||
(map[i + 1] << 0x3) |
|
||||
(map[i + 2] << 0x6) |
|
||||
(map[i + 3] << 0x9) |
|
||||
(map[i + 4] << 0xc) |
|
||||
(map[i + 5] << 0xf) |
|
||||
(map[i + 6] << 0x12) |
|
||||
(map[i + 7] << 0x15));
|
||||
|
||||
qdf_mem_copy(&val[cnt], &value, 3);
|
||||
cnt += 3;
|
||||
}
|
||||
|
||||
for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
|
||||
regval = *(uint32_t *)(val + i);
|
||||
HAL_REG_WRITE(soc, addr,
|
||||
(regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
|
||||
addr += 4;
|
||||
}
|
||||
|
||||
/* Diasble read/write access */
|
||||
regval = HAL_REG_READ(soc, cmn_reg_addr);
|
||||
regval &=
|
||||
~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
|
||||
|
||||
HAL_REG_WRITE(soc, cmn_reg_addr, regval);
|
||||
}
|
||||
|
||||
/**
|
||||
* hal_tx_update_dscp_tid_5018() - Update the dscp tid map table as
|
||||
updated by user
|
||||
* @soc: HAL SoC context
|
||||
* @map: DSCP-TID mapping table
|
||||
* @id : MAP ID
|
||||
* @dscp: DSCP_TID map index
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
static void hal_tx_update_dscp_tid_5018(struct hal_soc *soc, uint8_t tid,
|
||||
uint8_t id, uint8_t dscp)
|
||||
{
|
||||
uint32_t addr, addr1, cmn_reg_addr;
|
||||
uint32_t start_value = 0, end_value = 0;
|
||||
uint32_t regval;
|
||||
uint8_t end_bits = 0;
|
||||
uint8_t start_bits = 0;
|
||||
uint32_t start_index, end_index;
|
||||
|
||||
cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
|
||||
SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
|
||||
|
||||
addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
|
||||
SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET,
|
||||
id * NUM_WORDS_PER_DSCP_TID_TABLE);
|
||||
|
||||
start_index = dscp * HAL_TX_BITS_PER_TID;
|
||||
end_index = (start_index + (HAL_TX_BITS_PER_TID - 1))
|
||||
% HAL_TX_NUM_DSCP_REGISTER_SIZE;
|
||||
start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE;
|
||||
addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) /
|
||||
HAL_TX_NUM_DSCP_REGISTER_SIZE));
|
||||
|
||||
if (end_index < start_index) {
|
||||
end_bits = end_index + 1;
|
||||
start_bits = HAL_TX_BITS_PER_TID - end_bits;
|
||||
start_value = tid << start_index;
|
||||
end_value = tid >> start_bits;
|
||||
addr1 = addr + 4;
|
||||
} else {
|
||||
start_bits = HAL_TX_BITS_PER_TID - end_bits;
|
||||
start_value = tid << start_index;
|
||||
addr1 = 0;
|
||||
}
|
||||
|
||||
/* Enable read/write access */
|
||||
regval = HAL_REG_READ(soc, cmn_reg_addr);
|
||||
regval |=
|
||||
(1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
|
||||
|
||||
HAL_REG_WRITE(soc, cmn_reg_addr, regval);
|
||||
|
||||
regval = HAL_REG_READ(soc, addr);
|
||||
|
||||
if (end_index < start_index)
|
||||
regval &= (~0) >> start_bits;
|
||||
else
|
||||
regval &= ~(7 << start_index);
|
||||
|
||||
regval |= start_value;
|
||||
|
||||
HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
|
||||
|
||||
if (addr1) {
|
||||
regval = HAL_REG_READ(soc, addr1);
|
||||
regval &= (~0) << end_bits;
|
||||
regval |= end_value;
|
||||
|
||||
HAL_REG_WRITE(soc, addr1, (regval &
|
||||
HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
|
||||
}
|
||||
|
||||
/* Diasble read/write access */
|
||||
regval = HAL_REG_READ(soc, cmn_reg_addr);
|
||||
regval &=
|
||||
~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
|
||||
HAL_REG_WRITE(soc, cmn_reg_addr, regval);
|
||||
}
|
||||
|
||||
/**
|
||||
* hal_tx_desc_set_lmac_id_5018 - Set the lmac_id value
|
||||
* @desc: Handle to Tx Descriptor
|
||||
* @lmac_id: mac Id to ast matching
|
||||
* b00 – mac 0
|
||||
* b01 – mac 1
|
||||
* b10 – mac 2
|
||||
* b11 – all macs (legacy HK way)
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
static void hal_tx_desc_set_lmac_id_5018(void *desc, uint8_t lmac_id)
|
||||
{
|
||||
HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |=
|
||||
HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id);
|
||||
}
|
||||
236
hif/src/qca5018def.c
Normal file
236
hif/src/qca5018def.c
Normal file
|
|
@ -0,0 +1,236 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2020 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "qdf_module.h"
|
||||
|
||||
#if defined(QCA5018_HEADERS_DEF)
|
||||
|
||||
#undef UMAC
|
||||
#define WLAN_HEADERS 1
|
||||
|
||||
#include "wcss_version.h"
|
||||
#include "wcss_seq_hwiobase.h"
|
||||
#include "wfss_ce_reg_seq_hwioreg.h"
|
||||
|
||||
#define MISSING 0
|
||||
|
||||
#define SOC_RESET_CONTROL_OFFSET MISSING
|
||||
#define GPIO_PIN0_OFFSET MISSING
|
||||
#define GPIO_PIN1_OFFSET MISSING
|
||||
#define GPIO_PIN0_CONFIG_MASK MISSING
|
||||
#define GPIO_PIN1_CONFIG_MASK MISSING
|
||||
#define LOCAL_SCRATCH_OFFSET 0x18
|
||||
#define GPIO_PIN10_OFFSET MISSING
|
||||
#define GPIO_PIN11_OFFSET MISSING
|
||||
#define GPIO_PIN12_OFFSET MISSING
|
||||
#define GPIO_PIN13_OFFSET MISSING
|
||||
#define MBOX_BASE_ADDRESS MISSING
|
||||
#define INT_STATUS_ENABLE_ERROR_LSB MISSING
|
||||
#define INT_STATUS_ENABLE_ERROR_MASK MISSING
|
||||
#define INT_STATUS_ENABLE_CPU_LSB MISSING
|
||||
#define INT_STATUS_ENABLE_CPU_MASK MISSING
|
||||
#define INT_STATUS_ENABLE_COUNTER_LSB MISSING
|
||||
#define INT_STATUS_ENABLE_COUNTER_MASK MISSING
|
||||
#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
|
||||
#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
|
||||
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
|
||||
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
|
||||
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
|
||||
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
|
||||
#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
|
||||
#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
|
||||
#define INT_STATUS_ENABLE_ADDRESS MISSING
|
||||
#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
|
||||
#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
|
||||
#define HOST_INT_STATUS_ADDRESS MISSING
|
||||
#define CPU_INT_STATUS_ADDRESS MISSING
|
||||
#define ERROR_INT_STATUS_ADDRESS MISSING
|
||||
#define ERROR_INT_STATUS_WAKEUP_MASK MISSING
|
||||
#define ERROR_INT_STATUS_WAKEUP_LSB MISSING
|
||||
#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
|
||||
#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
|
||||
#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
|
||||
#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
|
||||
#define COUNT_DEC_ADDRESS MISSING
|
||||
#define HOST_INT_STATUS_CPU_MASK MISSING
|
||||
#define HOST_INT_STATUS_CPU_LSB MISSING
|
||||
#define HOST_INT_STATUS_ERROR_MASK MISSING
|
||||
#define HOST_INT_STATUS_ERROR_LSB MISSING
|
||||
#define HOST_INT_STATUS_COUNTER_MASK MISSING
|
||||
#define HOST_INT_STATUS_COUNTER_LSB MISSING
|
||||
#define RX_LOOKAHEAD_VALID_ADDRESS MISSING
|
||||
#define WINDOW_DATA_ADDRESS MISSING
|
||||
#define WINDOW_READ_ADDR_ADDRESS MISSING
|
||||
#define WINDOW_WRITE_ADDR_ADDRESS MISSING
|
||||
/* GPIO Register */
|
||||
#define GPIO_ENABLE_W1TS_LOW_ADDRESS MISSING
|
||||
#define GPIO_PIN0_CONFIG_LSB MISSING
|
||||
#define GPIO_PIN0_PAD_PULL_LSB MISSING
|
||||
#define GPIO_PIN0_PAD_PULL_MASK MISSING
|
||||
/* SI reg */
|
||||
#define SI_CONFIG_ERR_INT_MASK MISSING
|
||||
#define SI_CONFIG_ERR_INT_LSB MISSING
|
||||
|
||||
#define RTC_SOC_BASE_ADDRESS MISSING
|
||||
#define RTC_WMAC_BASE_ADDRESS MISSING
|
||||
#define SOC_CORE_BASE_ADDRESS MISSING
|
||||
#define WLAN_MAC_BASE_ADDRESS MISSING
|
||||
#define GPIO_BASE_ADDRESS MISSING
|
||||
#define ANALOG_INTF_BASE_ADDRESS MISSING
|
||||
#define CE0_BASE_ADDRESS MISSING
|
||||
#define CE1_BASE_ADDRESS MISSING
|
||||
#define CE_COUNT 12
|
||||
#define CE_WRAPPER_BASE_ADDRESS MISSING
|
||||
#define SI_BASE_ADDRESS MISSING
|
||||
#define DRAM_BASE_ADDRESS MISSING
|
||||
|
||||
#define WLAN_SYSTEM_SLEEP_DISABLE_LSB MISSING
|
||||
#define WLAN_SYSTEM_SLEEP_DISABLE_MASK MISSING
|
||||
#define CLOCK_CONTROL_OFFSET MISSING
|
||||
#define CLOCK_CONTROL_SI0_CLK_MASK MISSING
|
||||
#define RESET_CONTROL_SI0_RST_MASK MISSING
|
||||
#define WLAN_RESET_CONTROL_OFFSET MISSING
|
||||
#define WLAN_RESET_CONTROL_COLD_RST_MASK MISSING
|
||||
#define WLAN_RESET_CONTROL_WARM_RST_MASK MISSING
|
||||
#define CPU_CLOCK_OFFSET MISSING
|
||||
|
||||
#define CPU_CLOCK_STANDARD_LSB MISSING
|
||||
#define CPU_CLOCK_STANDARD_MASK MISSING
|
||||
#define LPO_CAL_ENABLE_LSB MISSING
|
||||
#define LPO_CAL_ENABLE_MASK MISSING
|
||||
#define WLAN_SYSTEM_SLEEP_OFFSET MISSING
|
||||
|
||||
#define SOC_CHIP_ID_ADDRESS MISSING
|
||||
#define SOC_CHIP_ID_REVISION_MASK MISSING
|
||||
#define SOC_CHIP_ID_REVISION_LSB MISSING
|
||||
#define SOC_CHIP_ID_REVISION_MSB MISSING
|
||||
|
||||
#define FW_IND_EVENT_PENDING MISSING
|
||||
#define FW_IND_INITIALIZED MISSING
|
||||
|
||||
#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
|
||||
#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
|
||||
#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
|
||||
#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
|
||||
#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB MISSING
|
||||
#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB MISSING
|
||||
#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB MISSING
|
||||
#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB MISSING
|
||||
|
||||
#define SR_WR_INDEX_ADDRESS MISSING
|
||||
#define DST_WATERMARK_ADDRESS MISSING
|
||||
|
||||
#define DST_WR_INDEX_ADDRESS MISSING
|
||||
#define SRC_WATERMARK_ADDRESS MISSING
|
||||
#define SRC_WATERMARK_LOW_MASK MISSING
|
||||
#define SRC_WATERMARK_HIGH_MASK MISSING
|
||||
#define DST_WATERMARK_LOW_MASK MISSING
|
||||
#define DST_WATERMARK_HIGH_MASK MISSING
|
||||
#define CURRENT_SRRI_ADDRESS MISSING
|
||||
#define CURRENT_DRRI_ADDRESS MISSING
|
||||
#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK MISSING
|
||||
#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK MISSING
|
||||
#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK MISSING
|
||||
#define HOST_IS_DST_RING_LOW_WATERMARK_MASK MISSING
|
||||
#define HOST_IS_ADDRESS MISSING
|
||||
#define MISC_IS_ADDRESS MISSING
|
||||
#define HOST_IS_COPY_COMPLETE_MASK MISSING
|
||||
#define CE_WRAPPER_BASE_ADDRESS MISSING
|
||||
#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS MISSING
|
||||
#define CE_DDR_ADDRESS_FOR_RRI_LOW MISSING
|
||||
#define CE_DDR_ADDRESS_FOR_RRI_HIGH MISSING
|
||||
|
||||
#define HOST_IE_ADDRESS \
|
||||
HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(\
|
||||
WFSS_CE_COMMON_REG_REG_BASE)
|
||||
#define HOST_IE_REG1_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT
|
||||
#define HOST_IE_ADDRESS_2 \
|
||||
HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(\
|
||||
WFSS_CE_COMMON_REG_REG_BASE)
|
||||
#define HOST_IE_REG2_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT
|
||||
#define HOST_IE_ADDRESS_3 \
|
||||
HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(\
|
||||
WFSS_CE_COMMON_REG_REG_BASE)
|
||||
#define HOST_IE_REG3_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT
|
||||
|
||||
#define HOST_IE_COPY_COMPLETE_MASK MISSING
|
||||
#define SR_BA_ADDRESS MISSING
|
||||
#define SR_BA_ADDRESS_HIGH MISSING
|
||||
#define SR_SIZE_ADDRESS MISSING
|
||||
#define CE_CTRL1_ADDRESS MISSING
|
||||
#define CE_CTRL1_DMAX_LENGTH_MASK MISSING
|
||||
#define DR_BA_ADDRESS MISSING
|
||||
#define DR_BA_ADDRESS_HIGH MISSING
|
||||
#define DR_SIZE_ADDRESS MISSING
|
||||
#define CE_CMD_REGISTER MISSING
|
||||
#define CE_MSI_ADDRESS MISSING
|
||||
#define CE_MSI_ADDRESS_HIGH MISSING
|
||||
#define CE_MSI_DATA MISSING
|
||||
#define CE_MSI_ENABLE_BIT MISSING
|
||||
#define MISC_IE_ADDRESS MISSING
|
||||
#define MISC_IS_AXI_ERR_MASK MISSING
|
||||
#define MISC_IS_DST_ADDR_ERR_MASK MISSING
|
||||
#define MISC_IS_SRC_LEN_ERR_MASK MISSING
|
||||
#define MISC_IS_DST_MAX_LEN_VIO_MASK MISSING
|
||||
#define MISC_IS_DST_RING_OVERFLOW_MASK MISSING
|
||||
#define MISC_IS_SRC_RING_OVERFLOW_MASK MISSING
|
||||
#define SRC_WATERMARK_LOW_LSB MISSING
|
||||
#define SRC_WATERMARK_HIGH_LSB MISSING
|
||||
#define DST_WATERMARK_LOW_LSB MISSING
|
||||
#define DST_WATERMARK_HIGH_LSB MISSING
|
||||
#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK MISSING
|
||||
#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB MISSING
|
||||
#define CE_CTRL1_DMAX_LENGTH_LSB MISSING
|
||||
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK MISSING
|
||||
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK MISSING
|
||||
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB MISSING
|
||||
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB MISSING
|
||||
#define CE_CTRL1_IDX_UPD_EN_MASK MISSING
|
||||
#define CE_WRAPPER_DEBUG_OFFSET MISSING
|
||||
#define CE_WRAPPER_DEBUG_SEL_MSB MISSING
|
||||
#define CE_WRAPPER_DEBUG_SEL_LSB MISSING
|
||||
#define CE_WRAPPER_DEBUG_SEL_MASK MISSING
|
||||
#define CE_DEBUG_OFFSET MISSING
|
||||
#define CE_DEBUG_SEL_MSB MISSING
|
||||
#define CE_DEBUG_SEL_LSB MISSING
|
||||
#define CE_DEBUG_SEL_MASK MISSING
|
||||
#define CE0_BASE_ADDRESS MISSING
|
||||
#define CE1_BASE_ADDRESS MISSING
|
||||
#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES MISSING
|
||||
#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS MISSING
|
||||
|
||||
#define QCA5018_BOARD_DATA_SZ MISSING
|
||||
#define QCA5018_BOARD_EXT_DATA_SZ MISSING
|
||||
|
||||
#define MY_TARGET_DEF QCA5018_TARGETDEF
|
||||
#define MY_HOST_DEF QCA5018_HOSTDEF
|
||||
#define MY_CEREG_DEF QCA5018_CE_TARGETDEF
|
||||
#define MY_TARGET_BOARD_DATA_SZ QCA5018_BOARD_DATA_SZ
|
||||
#define MY_TARGET_BOARD_EXT_DATA_SZ QCA5018_BOARD_EXT_DATA_SZ
|
||||
#include "targetdef.h"
|
||||
#include "hostdef.h"
|
||||
qdf_export_symbol(QCA5018_CE_TARGETDEF);
|
||||
#else
|
||||
#include "common_drv.h"
|
||||
#include "targetdef.h"
|
||||
#include "hostdef.h"
|
||||
struct targetdef_s *QCA5018_TARGETDEF;
|
||||
struct hostdef_s *QCA5018_HOSTDEF;
|
||||
#endif /*QCA5018_HEADERS_DEF */
|
||||
qdf_export_symbol(QCA5018_TARGETDEF);
|
||||
qdf_export_symbol(QCA5018_HOSTDEF);
|
||||
Loading…
Reference in a new issue