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[ARM] Separate VIC (vectored interrupt controller) support from Versatile

Browse source 
Other machines may wish to make use of the VIC support code, so
move it to arch/arm/common.

Signed-off-by: Russell King <[email protected]>
This commit is contained in:
Russell King 2006-01-13 21:30:48 +00:00 • committed by Russell King
commit fa0fe48fcc
8 changed files with 151 additions and 77 deletions
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1
include/asm-arm/arch-versatile/entry-macro.S
View file

@ -8,6 +8,7 @@
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware.h>
#include <asm/hardware/vic.h>
.macro disable_fiq
.endm

23
include/asm-arm/arch-versatile/platform.h
View file

@ -293,26 +293,7 @@
* VERSATILE_SYS_IC
*
*/
#define VIC_IRQ_STATUS 0
#define VIC_FIQ_STATUS 0x04
#define VIC_IRQ_RAW_STATUS 0x08
#define VIC_INT_SELECT 0x0C /* 1 = FIQ, 0 = IRQ */
#define VIC_IRQ_ENABLE 0x10 /* 1 = enable, 0 = disable */
#define VIC_IRQ_ENABLE_CLEAR 0x14
#define VIC_IRQ_SOFT 0x18
#define VIC_IRQ_SOFT_CLEAR 0x1C
#define VIC_PROTECT 0x20
#define VIC_VECT_ADDR 0x30
#define VIC_DEF_VECT_ADDR 0x34
#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */
#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */
#define VIC_ITCR 0x300 /* VIC test control register */
#define VIC_FIQ_RAW_STATUS 0x08
#define VIC_FIQ_ENABLE 0x10 /* 1 = enable, 0 = disable */
#define VIC_FIQ_ENABLE_CLEAR 0x14
#define VIC_FIQ_SOFT 0x18
#define VIC_FIQ_SOFT_CLEAR 0x1C
/* VIC definitions in include/asm-arm/hardware/vic.h */
#define SIC_IRQ_STATUS 0
#define SIC_IRQ_RAW_STATUS 0x04
@ -325,8 +306,6 @@
#define SIC_INT_PIC_ENABLES 0x20 /* set interrupt pass through bits */
#define SIC_INT_PIC_ENABLEC 0x24 /* Clear interrupt pass through bits */
#define VICVectCntl_Enable (1 << 5)
/* ------------------------------------------------------------------------
* Interrupts - bit assignment (primary)
* ------------------------------------------------------------------------

45
include/asm-arm/hardware/vic.h Normal file
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@ -0,0 +1,45 @@
/*
* linux/include/asm-arm/hardware/vic.h
*
* Copyright (c) ARM Limited 2003. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARM_HARDWARE_VIC_H
#define __ASM_ARM_HARDWARE_VIC_H
#define VIC_IRQ_STATUS 0x00
#define VIC_FIQ_STATUS 0x04
#define VIC_RAW_STATUS 0x08
#define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */
#define VIC_INT_ENABLE 0x10 /* 1 = enable, 0 = disable */
#define VIC_INT_ENABLE_CLEAR 0x14
#define VIC_INT_SOFT 0x18
#define VIC_INT_SOFT_CLEAR 0x1c
#define VIC_PROTECT 0x20
#define VIC_VECT_ADDR 0x30
#define VIC_DEF_VECT_ADDR 0x34
#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */
#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */
#define VIC_ITCR 0x300 /* VIC test control register */
#define VIC_VECT_CNTL_ENABLE (1 << 5)
#ifndef __ASSEMBLY__
void vic_init(void __iomem *base, u32 vic_sources);
#endif
#endif