From 7e0b238dd5fc2de8f0752fd894972f973683263d Mon Sep 17 00:00:00 2001 From: Ping Jiang Date: Tue, 26 Jan 2021 14:09:33 +0800 Subject: [PATCH] ARM: dts: msm: Add device nodes for FastRPC and CDSP Loader for SA8155 Add fastrpc device tree nodes for CDSP, ADSP and SDSP for SA8155. Add cdsp loader device tree node for SA8155. Change-Id: I0714079ca6307b8dbc5b8e9aa0804306c2d05b07 --- qcom/sm8150-v2.dtsi | 38 +++++++++++ qcom/sm8150.dtsi | 161 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 199 insertions(+) diff --git a/qcom/sm8150-v2.dtsi b/qcom/sm8150-v2.dtsi index d2877407f6e0..0be2903440f7 100644 --- a/qcom/sm8150-v2.dtsi +++ b/qcom/sm8150-v2.dtsi @@ -297,6 +297,44 @@ 0x0a44 0x03 0x0>; }; +&msm_fastrpc { + qcom,msm_fastrpc_compute_cb1 { + iommus = <&apps_smmu 0x1001 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb2 { + iommus = <&apps_smmu 0x1002 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb3 { + iommus = <&apps_smmu 0x1003 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb4 { + iommus = <&apps_smmu 0x1004 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb5 { + iommus = <&apps_smmu 0x1005 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb6 { + iommus = <&apps_smmu 0x1006 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb7 { + iommus = <&apps_smmu 0x1007 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb8 { + iommus = <&apps_smmu 0x1008 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb9 { + iommus = <&apps_smmu 0x1009 0x0460>; + }; +}; + /* GPU overrides */ &msm_gpu { /* Updated chip ID */ diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 1108f8366fdd..f97e756b92bf 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1618,6 +1618,167 @@ }; }; + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + }; + + msm_fastrpc: qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,fastrpc-adsp-audio-pdr; + qcom,rpc-latency-us = <235>; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1401 0x2040>, + <&apps_smmu 0x1421 0x0>, + <&apps_smmu 0x2001 0x420>, + <&apps_smmu 0x2041 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x4 0x3440>, + <&apps_smmu 0x24 0x3400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x5 0x3440>, + <&apps_smmu 0x25 0x3400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x6 0x3460>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb7 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x7 0x3460>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb8 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x8 0x3460>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x2 0x3440>, + <&apps_smmu 0x22 0x3400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x3 0x3440>, + <&apps_smmu 0x1423 0x0>, + <&apps_smmu 0x2023 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x9 0x3460>; + qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1b23 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1b24 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1b25 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb13 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "sdsprpc-smd"; + iommus = <&apps_smmu 0x5a1 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb14 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "sdsprpc-smd"; + iommus = <&apps_smmu 0x5a2 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb15 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "sdsprpc-smd"; + iommus = <&apps_smmu 0x5a3 0x0>; + shared-cb = <4>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent-hint-cached; + }; + }; + qcom,glink { compatible = "qcom,glink"; #address-cells = <1>;