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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: dts: msm: create sde-display-common device tree on Shima
Separate common SDE display bindings in sde-display-common dt file to avoid unwanted duplications between VM variants of the SDE display files on Shima target. Change-Id: Ibcb285e855a5474f9308f55032389c63d4725357
This commit is contained in:
Rajeev Nandan
Ritesh Kumar
parent
d408887b2e
commit
fa987c0307
2 changed files with 206 additions and 189 deletions
140
display/shima-sde-display-common.dtsi
Normal file
140
display/shima-sde-display-common.dtsi
Normal file
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@ -0,0 +1,140 @@
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#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi"
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#include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi"
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#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi"
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#include "dsi-panel-sim-video.dtsi"
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#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
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&soc {
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dsi_panel_pwr_supply: dsi_panel_pwr_supply {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,panel-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vddio";
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qcom,supply-min-voltage = <1920000>;
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qcom,supply-max-voltage = <1920000>;
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qcom,supply-enable-load = <60700>;
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qcom,supply-disable-load = <80>;
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qcom,supply-post-on-sleep = <20>;
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};
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qcom,panel-supply-entry@1 {
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reg = <1>;
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qcom,supply-name = "vdd";
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qcom,supply-min-voltage = <3000000>;
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qcom,supply-max-voltage = <3000000>;
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qcom,supply-enable-load = <30000>;
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qcom,supply-disable-load = <0>;
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qcom,supply-post-on-sleep = <0>;
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};
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qcom,panel-supply-entry@2 {
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reg = <2>;
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qcom,supply-name = "lab";
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qcom,supply-min-voltage = <4600000>;
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qcom,supply-max-voltage = <6000000>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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qcom,panel-supply-entry@3 {
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reg = <3>;
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qcom,supply-name = "ibb";
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qcom,supply-min-voltage = <4600000>;
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qcom,supply-max-voltage = <6000000>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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qcom,supply-post-on-sleep = <20>;
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};
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};
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sde_dsi: qcom,dsi-display-primary {
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compatible = "qcom,dsi-display";
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label = "primary";
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qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
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qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
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qcom,mdp = <&mdss_mdp>;
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};
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sde_dsi1: qcom,dsi-display-secondary {
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compatible = "qcom,dsi-display";
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label = "secondary";
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qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
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qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
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qcom,mdp = <&mdss_mdp>;
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};
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};
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&dsi_r66451_amoled_video {
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qcom,dsi-supported-dfps-list = <120 90 60 48>;
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qcom,mdss-dsi-pan-enable-dynamic-fps;
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qcom,mdss-dsi-min-refresh-rate = <48>;
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qcom,mdss-dsi-max-refresh-rate = <120>;
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qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
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qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
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qcom,mdss-dsi-display-timings {
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timing@0 {
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qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08
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08 05 02 04 00 17 0c];
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qcom,display-topology = <2 2 1>;
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qcom,default-topology-index = <0>;
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};
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};
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};
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&dsi_r66451_amoled_60hz_video {
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qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
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qcom,mdss-dsi-display-timings {
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timing@0 {
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qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04
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04 03 02 04 00 0e 09];
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qcom,display-topology = <2 2 1>;
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qcom,default-topology-index = <0>;
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};
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};
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};
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&dsi_r66451_amoled_cmd {
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qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
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qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
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qcom,mdss-dsi-display-timings {
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timing@0 {
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qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04
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04 03 02 04 00 0e 09];
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qcom,display-topology = <2 2 1>;
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qcom,default-topology-index = <0>;
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};
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timing@1 {
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qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06
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06 06 02 04 00 14 0a];
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qcom,display-topology = <2 2 1>;
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qcom,default-topology-index = <0>;
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};
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timing@2 {
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qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07
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07 08 02 04 00 19 0c];
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qcom,display-topology = <2 2 1>;
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qcom,default-topology-index = <0>;
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};
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};
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};
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&dsi_sim_vid {
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qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
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qcom,mdss-dsi-display-timings {
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timing@0 {
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qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01
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01 01 02 04 00 06 06];
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qcom,display-topology = <1 0 1>,
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<2 0 1>;
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qcom,default-topology-index = <0>;
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};
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};
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};
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@ -1,134 +1,6 @@
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#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi"
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#include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi"
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#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi"
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#include "dsi-panel-sim-video.dtsi"
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#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
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#include "shima-sde-display-common.dtsi"
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&soc {
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dsi_panel_pwr_supply: dsi_panel_pwr_supply {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,panel-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vddio";
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qcom,supply-min-voltage = <1920000>;
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qcom,supply-max-voltage = <1920000>;
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qcom,supply-enable-load = <60700>;
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qcom,supply-disable-load = <80>;
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qcom,supply-post-on-sleep = <20>;
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};
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qcom,panel-supply-entry@1 {
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reg = <1>;
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qcom,supply-name = "vdd";
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qcom,supply-min-voltage = <3000000>;
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qcom,supply-max-voltage = <3000000>;
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qcom,supply-enable-load = <30000>;
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qcom,supply-disable-load = <0>;
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qcom,supply-post-on-sleep = <0>;
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};
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qcom,panel-supply-entry@2 {
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reg = <2>;
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qcom,supply-name = "lab";
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qcom,supply-min-voltage = <4600000>;
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qcom,supply-max-voltage = <6000000>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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qcom,panel-supply-entry@3 {
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reg = <3>;
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qcom,supply-name = "ibb";
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qcom,supply-min-voltage = <4600000>;
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qcom,supply-max-voltage = <6000000>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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qcom,supply-post-on-sleep = <20>;
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};
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};
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sde_dsi: qcom,dsi-display-primary {
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compatible = "qcom,dsi-display";
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label = "primary";
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qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
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qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
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clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
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<&mdss_dsi_phy0 PCLK_MUX_0_CLK>,
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<&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>,
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<&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>,
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<&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>,
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<&mdss_dsi_phy0 PCLK_SRC_0_CLK>,
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<&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>,
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<&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>,
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<&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>,
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<&mdss_dsi_phy1 PCLK_MUX_1_CLK>,
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<&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>,
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<&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>,
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<&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>,
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<&mdss_dsi_phy1 PCLK_SRC_1_CLK>,
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<&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>,
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<&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>;
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clock-names = "mux_byte_clk0", "mux_pixel_clk0",
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"cphy_byte_clk0", "cphy_pixel_clk0",
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"src_byte_clk0", "src_pixel_clk0",
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"shadow_byte_clk0", "shadow_pixel_clk0",
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"mux_byte_clk1", "mux_pixel_clk1",
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"cphy_byte_clk1", "cphy_pixel_clk1",
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"src_byte_clk1", "src_pixel_clk1",
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"shadow_byte_clk1", "shadow_pixel_clk1";
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pinctrl-names = "panel_active", "panel_suspend";
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pinctrl-0 = <&sde_dsi_active &sde_te_active>;
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pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
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qcom,platform-te-gpio = <&tlmm 82 0>;
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qcom,panel-te-source = <0>;
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vddio-supply = <&L12C>;
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vdd-supply = <&L13C>;
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lab-supply = <&ab_vreg>;
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ibb-supply = <&ibb_vreg>;
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qcom,mdp = <&mdss_mdp>;
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};
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sde_dsi1: qcom,dsi-display-secondary {
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compatible = "qcom,dsi-display";
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label = "secondary";
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qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
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qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
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clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
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<&mdss_dsi_phy0 PCLK_MUX_0_CLK>,
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<&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>,
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<&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>,
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<&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>,
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<&mdss_dsi_phy1 PCLK_MUX_1_CLK>,
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<&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>,
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<&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>;
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clock-names = "mux_byte_clk0", "mux_pixel_clk0",
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"cphy_byte_clk0", "cphy_pixel_clk0",
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"mux_byte_clk1", "mux_pixel_clk1",
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"cphy_byte_clk1", "cphy_pixel_clk1";
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pinctrl-names = "panel_active", "panel_suspend";
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pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;
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pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>;
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qcom,platform-te-gpio = <&tlmm 83 0>;
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qcom,panel-te-source = <1>;
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vddio-supply = <&L12C>;
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vdd-supply = <&L13C>;
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qcom,mdp = <&mdss_mdp>;
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};
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sde_wb: qcom,wb-display@0 {
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compatible = "qcom,wb-display";
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cell-index = <0>;
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@ -136,6 +8,71 @@
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};
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};
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&sde_dsi {
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clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
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<&mdss_dsi_phy0 PCLK_MUX_0_CLK>,
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<&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>,
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<&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>,
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<&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>,
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<&mdss_dsi_phy0 PCLK_SRC_0_CLK>,
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<&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>,
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<&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>,
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<&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>,
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<&mdss_dsi_phy1 PCLK_MUX_1_CLK>,
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<&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>,
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<&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>,
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<&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>,
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<&mdss_dsi_phy1 PCLK_SRC_1_CLK>,
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<&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>,
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<&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>;
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clock-names = "mux_byte_clk0", "mux_pixel_clk0",
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"cphy_byte_clk0", "cphy_pixel_clk0",
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"src_byte_clk0", "src_pixel_clk0",
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"shadow_byte_clk0", "shadow_pixel_clk0",
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"mux_byte_clk1", "mux_pixel_clk1",
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"cphy_byte_clk1", "cphy_pixel_clk1",
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"src_byte_clk1", "src_pixel_clk1",
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"shadow_byte_clk1", "shadow_pixel_clk1";
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pinctrl-names = "panel_active", "panel_suspend";
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pinctrl-0 = <&sde_dsi_active &sde_te_active>;
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pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
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qcom,platform-te-gpio = <&tlmm 82 0>;
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qcom,panel-te-source = <0>;
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vddio-supply = <&L12C>;
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vdd-supply = <&L13C>;
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lab-supply = <&ab_vreg>;
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ibb-supply = <&ibb_vreg>;
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};
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&sde_dsi1 {
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clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
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<&mdss_dsi_phy0 PCLK_MUX_0_CLK>,
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<&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>,
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<&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>,
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<&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>,
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<&mdss_dsi_phy1 PCLK_MUX_1_CLK>,
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<&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>,
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<&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>;
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clock-names = "mux_byte_clk0", "mux_pixel_clk0",
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"cphy_byte_clk0", "cphy_pixel_clk0",
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"mux_byte_clk1", "mux_pixel_clk1",
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"cphy_byte_clk1", "cphy_pixel_clk1";
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pinctrl-names = "panel_active", "panel_suspend";
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pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;
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pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>;
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qcom,platform-te-gpio = <&tlmm 83 0>;
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qcom,panel-te-source = <1>;
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vddio-supply = <&L12C>;
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vdd-supply = <&L13C>;
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};
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&mdss_mdp {
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connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi
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&sde_dsi1>;
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@ -148,20 +85,6 @@
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qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
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qcom,mdss-dsi-panel-status-value = <0x1c>;
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qcom,mdss-dsi-panel-status-read-length = <1>;
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qcom,dsi-supported-dfps-list = <120 90 60 48>;
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qcom,mdss-dsi-pan-enable-dynamic-fps;
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qcom,mdss-dsi-min-refresh-rate = <48>;
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qcom,mdss-dsi-max-refresh-rate = <120>;
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qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
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qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
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qcom,mdss-dsi-display-timings {
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timing@0 {
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qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08
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08 05 02 04 00 17 0c];
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qcom,display-topology = <2 2 1>;
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qcom,default-topology-index = <0>;
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};
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};
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};
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&dsi_r66451_amoled_60hz_video {
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||||
|
|
@ -171,15 +94,6 @@
|
|||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x1c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04
|
||||
04 03 02 04 00 0e 09];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_r66451_amoled_cmd {
|
||||
|
|
@ -189,41 +103,4 @@
|
|||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x1c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04
|
||||
04 03 02 04 00 0e 09];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06
|
||||
06 06 02 04 00 14 0a];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01
|
||||
01 01 02 04 00 06 06];
|
||||
qcom,display-topology = <1 0 1>,
|
||||
<2 0 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue