From facf1631a4ae43240db4b0c40c10f22d79cfd733 Mon Sep 17 00:00:00 2001 From: Ajay Prathi Date: Wed, 13 Jan 2021 21:37:30 +0530 Subject: [PATCH] msm: pci: Update VREG info fron DT Assign Voltage regulator max and min values from DT. Change-Id: Ib1e58894b4498ed7f196cb548ca7bd170b5c3455 Signed-off-by: Ajay Prathi --- drivers/pci/controller/pci-msm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c index 8fec768057ad..f3dff285c487 100644 --- a/drivers/pci/controller/pci-msm.c +++ b/drivers/pci/controller/pci-msm.c @@ -173,6 +173,7 @@ #define MAX_PROP_SIZE (32) #define MAX_RC_NAME_LEN (15) #define MSM_PCIE_MAX_VREG (5) +#define MSM_PCIE_VREG_0P9 (2) #define MSM_PCIE_MAX_CLK (18) #define MSM_PCIE_MAX_PIPE_CLK (1) #define MAX_RC_NUM (4) @@ -770,6 +771,7 @@ struct msm_pcie_dev_t { struct msm_pcie_drv_info *drv_info; struct work_struct drv_enable_pc_work; struct work_struct drv_disable_pc_work; + int vreg_levels[3]; /* cache drv pc req from RC client, by default drv pc is enabled */ int drv_disable_pc_vote; @@ -5859,6 +5861,22 @@ static int msm_pcie_probe(struct platform_device *pdev) memcpy(pcie_dev->pipe_reset, msm_pcie_pipe_reset_info[rc_idx], sizeof(msm_pcie_pipe_reset_info[rc_idx])); + ret = of_property_read_u32_array(of_node, + "qcom,vreg-0.9-voltage-level", + (u32 *) pcie_dev->vreg_levels, + ARRAY_SIZE(pcie_dev->vreg_levels)); + if (ret) { + PCIE_DBG(pcie_dev, + "vreg-0.9-voltage-level missing, using default values\n"); + } else { + pcie_dev->vreg[MSM_PCIE_VREG_0P9].max_v = + pcie_dev->vreg_levels[0]; + pcie_dev->vreg[MSM_PCIE_VREG_0P9].min_v = + pcie_dev->vreg_levels[1]; + pcie_dev->vreg[MSM_PCIE_VREG_0P9].opt_mode = + pcie_dev->vreg_levels[2]; + } + for (i = 0; i < PCIE_CONF_SPACE_DW; i++) pcie_dev->rc_shadow[i] = PCIE_CLEAR; for (i = 0; i < MAX_DEVICE_NUM; i++)