From 71f615345a01d3e85399b8c53516352ad14e98d6 Mon Sep 17 00:00:00 2001 From: Prabhanjan Kandula Date: Wed, 3 Jun 2020 01:19:27 -0700 Subject: [PATCH] disp: msm: sde: fix system cache feature enable In current driver if client did not reset system cache crtc property, system cache write state is on forever and breaks the system cache feature. This change restricts entering into cache write state only if it's commit right after idle notify. This change also adds event logs to capture system cache feature state changes. Change-Id: Ie46fc9113f752ed8989dab99301690a13003b00b Signed-off-by: Prabhanjan Kandula --- msm/sde/sde_crtc.c | 6 +++++- msm/sde/sde_plane.c | 3 +++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/msm/sde/sde_crtc.c b/msm/sde/sde_crtc.c index 83e3935ab723..68086dfda610 100644 --- a/msm/sde/sde_crtc.c +++ b/msm/sde/sde_crtc.c @@ -3351,7 +3351,8 @@ static void sde_crtc_atomic_flush(struct drm_crtc *crtc, event_thread = &priv->event_thread[crtc->index]; idle_time = sde_crtc_get_property(cstate, CRTC_PROP_IDLE_TIMEOUT); - if (sde_crtc_get_property(cstate, CRTC_PROP_CACHE_STATE)) + if ((sde_crtc->cache_state == CACHE_STATE_PRE_CACHE) && + sde_crtc_get_property(cstate, CRTC_PROP_CACHE_STATE)) sde_crtc_static_img_control(crtc, CACHE_STATE_FRAME_WRITE, false); else @@ -6280,6 +6281,8 @@ void sde_crtc_static_img_control(struct drm_crtc *crtc, return; sde_crtc = to_sde_crtc(crtc); + if (sde_crtc->cache_state == state) + return; switch (state) { case CACHE_STATE_NORMAL: @@ -6395,6 +6398,7 @@ static void __sde_crtc_idle_notify_work(struct kthread_work *work) msm_mode_object_event_notify(&crtc->base, crtc->dev, &event, (u8 *)&ret); + SDE_EVT32(DRMID(crtc)); SDE_DEBUG("crtc[%d]: idle timeout notified\n", crtc->base.id); sde_crtc_static_img_control(crtc, CACHE_STATE_PRE_CACHE, false); diff --git a/msm/sde/sde_plane.c b/msm/sde/sde_plane.c index b38a2aa36bfe..7f4137d635ea 100644 --- a/msm/sde/sde_plane.c +++ b/msm/sde/sde_plane.c @@ -2833,6 +2833,9 @@ static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde, pstate->sc_cfg.type = SDE_SYS_CACHE_DISP; } + SDE_EVT32(DRMID(&psde->base), pstate->sc_cfg.rd_scid, + pstate->sc_cfg.rd_en, pstate->sc_cfg.rd_noallocate); + psde->pipe_hw->ops.setup_sys_cache( psde->pipe_hw, &pstate->sc_cfg); }