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clk: qcom: clk-alpha-pll: Add support for Trion print registers

Browse source 
Trion PLL print registers are required to get the PLL values
from the debugfs, thus add support for the same.

Change-Id: I622d8136b8c57388638409aaf8509fb104723a79
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das 2020-04-08 14:32:17 +05:30 • committed by Gerrit - the friendly Code Review server
commit fb511cfd80
1 changed files with 61 additions and 0 deletions
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61
drivers/clk/qcom/clk-alpha-pll.c
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@ -1114,6 +1114,63 @@ static int clk_trion_pll_prepare(struct clk_hw *hw)
return 0;
}
static void clk_trion_pll_list_registers(struct seq_file *f, struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
int size, i, val;
static struct clk_register_data data[] = {
{"PLL_MODE", PLL_OFF_MODE},
{"PLL_L_VAL", PLL_OFF_L_VAL},
{"PLL_CAL_L_VAL", PLL_OFF_CAL_L_VAL},
{"PLL_USER_CTL", PLL_OFF_USER_CTL},
{"PLL_USER_CTL_U", PLL_OFF_USER_CTL_U},
{"PLL_USER_CTL_U1", PLL_OFF_USER_CTL_U1},
{"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL},
{"PLL_CONFIG_CTL_U", PLL_OFF_CONFIG_CTL_U},
{"PLL_CONFIG_CTL_U1", PLL_OFF_CONFIG_CTL_U1},
{"PLL_TEST_CTL", PLL_OFF_TEST_CTL},
{"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U},
{"PLL_TEST_CTL_U1", PLL_OFF_TEST_CTL_U1},
{"PLL_STATUS", PLL_OFF_STATUS},
{"PLL_OPMODE", PLL_OFF_MODE},
{"PLL_ALPHA_VAL", PLL_OFF_ALPHA_VAL},
};
static struct clk_register_data data1[] = {
{"APSS_PLL_VOTE", 0x0},
};
size = ARRAY_SIZE(data);
for (i = 0; i < size; i++) {
regmap_read(pll->clkr.regmap, pll->offset +
pll->regs[data[i].offset], &val);
seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);
}
regmap_read(pll->clkr.regmap, pll->offset + pll->regs[data[0].offset],
&val);
if (val & PLL_FSM_ENA) {
regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
data1[0].offset, &val);
seq_printf(f, "%20s: 0x%.8x\n", data1[0].name, val);
}
}
static struct clk_regmap_ops clk_trion_pll_regmap_ops = {
.list_registers = &clk_trion_pll_list_registers,
};
static void clk_trion_pll_init(struct clk_hw *hw)
{
struct clk_regmap *rclk = to_clk_regmap(hw);
if (!rclk->ops)
rclk->ops = &clk_trion_pll_regmap_ops;
}
static int __zonda_pll_is_enabled(struct clk_alpha_pll *pll,
struct regmap *regmap)
{
@ -1657,6 +1714,8 @@ const struct clk_ops clk_trion_pll_ops = {
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.set_rate = clk_trion_pll_set_rate,
.debug_init = clk_common_debug_init,
.init = clk_trion_pll_init,
#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG
.list_rate_vdd_level = clk_list_rate_vdd_level,
#endif
@ -1673,6 +1732,8 @@ const struct clk_ops clk_trion_fixed_pll_ops = {
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.debug_init = clk_common_debug_init,
.init = clk_trion_pll_init,
#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG
.list_rate_vdd_level = clk_list_rate_vdd_level,
#endif