From c640c89e053e6ee45adaa1614bde52c3350a5cb2 Mon Sep 17 00:00:00 2001
From: Madhuri Medasani <mmedasan@qti.qualcomm.com>
Date: Wed, 7 Jul 2021 11:35:24 +0530
Subject: [PATCH] ARM: dts: msm: Mark PMIC QUPs as critical clock devices for
 BLAIR

To prevent deadlocks between the clock and regulator frameworks,
the QUP clocks used by I2C-connected PMICs must be enabled all
the time and not registered with the clock framework. Skipping
the registration short-circuits the I2C device's clock calls such
that they return success before grabbing the clock locks. Achieve
this behavior by setting GCC's qcom,critical-devices property.

Change-Id: Idf812aa1df3a21670b8e9c262548cbf5f528e41b
---
 qcom/holi-pmic-overlay-pm6125.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/qcom/holi-pmic-overlay-pm6125.dtsi b/qcom/holi-pmic-overlay-pm6125.dtsi
index 78a61af2db8f..dcc5af29e2da 100644
--- a/qcom/holi-pmic-overlay-pm6125.dtsi
+++ b/qcom/holi-pmic-overlay-pm6125.dtsi
@@ -330,6 +330,14 @@
 	};
 };
 
+/*
+ * Each QUP device that's a parent to PMIC must be listed as a critical device
+ * to GCC
+ */
+&gcc {
+	qcom,critical-devices = <&qupv3_se10_i2c>;
+};
+
 &qupv3_se10_i2c {
 	#address-cells = <1>;
 	#size-cells = <0>;