mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-11 15:11:48 -04:00
dtsi:init config to fix Penang vendor build error
add dtsi for new product penang5g Base on product milanf Change-Id: If75e8907316fd0dd2c7e15c07e105aec96d5c021 Signed-off-by: caoqian4 <caoqian4@motorola.com> Reviewed-on: https://gerrit.mot.com/2296531 SME-Granted: SME Approvals Granted SLTApproved: Slta Waiver Tested-by: Jira Key Reviewed-by: Xiangpo Zhao <zhaoxp3@motorola.com>
This commit is contained in:
caoqian4
panyq6
parent
13cab76257
commit
fb84e6206c
4 changed files with 504 additions and 0 deletions
38
qcom/blair-nopmi-penang-common-overlay.dtsi
Normal file
38
qcom/blair-nopmi-penang-common-overlay.dtsi
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@ -0,0 +1,38 @@
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/* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "blair-penang-common-overlay.dtsi"
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#include "blair-nopmi-moto-common-overlay.dtsi"
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#include "tcpc_config.dtsi"
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#include "discrete-rt-pd-manger.dtsi"
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#include "sgm7220.dtsi"
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#include "rt9426a.dtsi"
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#include "discrete_charging.dtsi"
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&qupv3_se8_i2c {
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status = "okay";
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oz8806@2f {
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compatible = "o2micro,oz8806";
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reg = <0x2f>;
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status = "okay";
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};
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cw2217@64 {
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compatible = "cellwise,cw2217";
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reg = <0x64>;
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status = "okay";
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df-serialnum = "SB18D33989";
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#include "bat_setting/CW_md50-scud-5000mah.dtsi"
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#include "bat_setting/CW_md50-amperex-5000mah.dtsi"
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};
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};
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21
qcom/blair-pm6125-penang-common-overlay.dtsi
Normal file
21
qcom/blair-pm6125-penang-common-overlay.dtsi
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@ -0,0 +1,21 @@
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/* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "blair-penang-common-overlay.dtsi"
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#include "blair-pm6125-moto-common-overlay.dtsi"
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&pm7250b_charger {
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dpdm-supply = <&usb2_phy0>;
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};
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&smb1394 {
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status = "disabled";
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};
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394
qcom/holi-audio-penang-overlay.dtsi
Normal file
394
qcom/holi-audio-penang-overlay.dtsi
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@ -0,0 +1,394 @@
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#include <dt-bindings/clock/qcom,audio-ext-clk.h>
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#include <dt-bindings/sound/qcom,bolero-clk-rsc.h>
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#include <dt-bindings/sound/audio-codec-port-types.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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&tlmm{
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aw882xx_irq_default: aw882xx_irq_default {
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mux {
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pins = "gpio59";
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function = "gpio";
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};
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config {
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pins = "gpio59";
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drive-strength = <2>; /* 2 MA */
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bias-pull-up;
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};
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};
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};
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&cdc_dmic01_gpios {
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status = "disabled";
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};
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&cdc_dmic23_gpios {
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status = "disabled";
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};
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&rx_swr_gpios {
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status = "okay";
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};
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&dai_mi2s0_rx {
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status = "okay";
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qcom,msm-mi2s-lines = <1>;
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};
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&dai_mi2s0_tx {
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status = "okay";
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qcom,msm-mi2s-lines = <0>;
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};
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&dai_mi2s1_rx {
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status = "okay";
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qcom,msm-mi2s-lines = <1>;
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};
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&dai_mi2s1_tx {
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status = "okay";
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qcom,msm-mi2s-lines = <2>;
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};
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&dai_mi2s2_rx {
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status = "okay";
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qcom,msm-mi2s-lines = <1>;
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};
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&dai_mi2s2_tx {
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status = "okay";
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qcom,msm-mi2s-lines = <0>;
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};
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&dai_mi2s3_rx {
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status = "okay";
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qcom,msm-mi2s-lines = <1>;
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};
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&dai_mi2s3_tx {
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status = "okay";
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qcom,msm-mi2s-lines = <0>;
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};
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&q6core {
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cdc_sec_mi2s_gpios: cdc_sec_mi2s_gpios {
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compatible = "qcom,msm-cdc-pinctrl";
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pinctrl-names = "aud_active", "aud_sleep";
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pinctrl-0 = <&lpi_i2s2_sck_active &lpi_i2s2_ws_active
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&lpi_i2s2_sd0_active &lpi_i2s2_sd1_active>;
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pinctrl-1 = <&lpi_i2s2_sck_sleep &lpi_i2s2_ws_sleep
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&lpi_i2s2_sd0_sleep &lpi_i2s2_sd1_sleep>;
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qcom,lpi-gpios;
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#gpio-cells = <0>;
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};
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};
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&bolero {
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qcom,num-macros = <3>;
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qcom,bolero-version = <5>;
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#address-cells = <1>;
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#size-cells = <1>;
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bolero-clk-rsc-mngr {
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compatible = "qcom,bolero-clk-rsc-mngr";
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qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>,
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<0x3004 0x3 0x1>, <0x3080 0x2 0x2>;
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qcom,rx_mclk_mode_muxsel = <0x0A5640D8>;
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qcom,va_mclk_mode_muxsel = <0x0A7A0000>;
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clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",
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"va_core_clk", "va_npl_clk";
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clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
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<&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
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<&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
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};
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va_macro: va-macro@A730000 {
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compatible = "qcom,va-macro";
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reg = <0xA730000 0x0>;
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clock-names = "lpass_audio_hw_vote";
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clocks = <&lpass_audio_hw_vote 0>;
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qcom,va-dmic-sample-rate = <600000>;
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qcom,default-clk-id = <TX_CORE_CLK>;
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qcom,is-used-swr-gpio = <1>;
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qcom,va-swr-gpios = <&va_swr_gpios>;
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swr0: va_swr_master {
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compatible = "qcom,swr-mstr";
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qcom,is_wcd937x = <1>;
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#address-cells = <2>;
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#size-cells = <0>;
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clock-names = "lpass_audio_hw_vote";
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clocks = <&lpass_audio_hw_vote 0>;
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qcom,swr_master_id = <3>;
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qcom,swrm-hctl-reg = <0x0A7EC100>;
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qcom,mipi-sdw-block-packing-mode = <1>;
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swrm-io-base = <0xA740000 0x0>;
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interrupts-extended =
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<&wakegic 5 IRQ_TYPE_LEVEL_HIGH>,
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<&tlmm 128 GPIO_ACTIVE_HIGH>;
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interrupt-names = "swr_master_irq", "swr_wake_irq";
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qcom,swr-num-ports = <3>;
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qcom,swr-port-mapping = <1 SWRM_TX1_CH1 0x1>,
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<1 SWRM_TX1_CH2 0x2>,
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<1 SWRM_TX1_CH3 0x4>, <1 SWRM_TX1_CH4 0x8>,
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<2 SWRM_TX2_CH1 0x1>, <2 SWRM_TX2_CH2 0x2>,
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<2 SWRM_TX2_CH3 0x4>, <2 SWRM_TX2_CH4 0x8>,
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<3 SWRM_TX3_CH1 0x1>, <3 SWRM_TX3_CH2 0x2>,
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<3 SWRM_TX3_CH3 0x4>, <3 SWRM_TX3_CH4 0x8>;
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qcom,swr-num-dev = <1>;
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qcom,swr-phy-dev-addr = <0x0A 0x01170223>,
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<0x08 0x58350223>,
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<0x08 0x58350222>,
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<0x08 0x58350221>,
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<0x08 0x58350220>;
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qcom,swr-clock-stop-mode0 = <1>;
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qcom,swr-mstr-irq-wakeup-capable = <1>;
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qcom,is-always-on = <1>;
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wcd937x_tx_slave: wcd937x-tx-slave {
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compatible = "qcom,wcd937x-slave";
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reg = <0x0A 0x01170223>;
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};
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};
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};
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tx_macro: tx-macro@A620000 {
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compatible = "qcom,tx-macro";
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reg = <0xA620000 0x0>;
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clock-names = "tx_core_clk", "tx_npl_clk";
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clocks = <&clock_audio_tx_1 0>,
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<&clock_audio_tx_2 0>;
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qcom,tx-dmic-sample-rate = <2400000>;
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qcom,is-used-swr-gpio = <0>;
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};
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rx_macro: rx-macro@A600000 {
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compatible = "qcom,rx-macro";
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reg = <0xA600000 0x0>;
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clock-names = "rx_core_clk", "rx_npl_clk";
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clocks = <&clock_audio_rx_1 0>,
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<&clock_audio_rx_2 0>;
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qcom,rx-swr-gpios = <&rx_swr_gpios>;
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qcom,rx_mclk_mode_muxsel = <0xA5640D8>;
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qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
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qcom,default-clk-id = <TX_CORE_CLK>;
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swr1: rx_swr_master {
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compatible = "qcom,swr-mstr";
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#address-cells = <2>;
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#size-cells = <0>;
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clock-names = "lpass_audio_hw_vote";
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clocks = <&lpass_audio_hw_vote 0>;
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qcom,swr_master_id = <2>;
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qcom,swrm-hctl-reg = <0x0A6A9098>;
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qcom,mipi-sdw-block-packing-mode = <1>;
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swrm-io-base = <0xA610000 0x0>;
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interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "swr_master_irq";
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qcom,swr-num-ports = <6>;
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qcom,swr-port-mapping = <1 HPH_L 0x1>,
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<1 HPH_R 0x2>, <2 CLSH 0x1>,
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<3 COMP_L 0x1>, <3 COMP_R 0x2>,
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<4 LO 0x1>, <5 DSD_L 0x1>,
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<5 DSD_R 0x2>, <6 PCM_OUT1 0x01>;
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qcom,swr-num-dev = <1>;
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qcom,swr-clock-stop-mode0 = <1>;
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wcd937x_rx_slave: wcd937x-rx-slave {
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compatible = "qcom,wcd937x-slave";
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reg = <0x0A 0x01170224>;
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};
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};
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};
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wcd937x_codec: wcd937x-codec {
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compatible = "qcom,wcd937x-codec";
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qcom,split-codec = <1>;
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qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
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<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
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<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
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<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
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<4 DSD_R 0x2 0 DSD_R>;
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qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>,
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<1 ADC2 0x1 0 SWRM_TX2_CH1>,
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<1 ADC3 0x2 0 SWRM_TX2_CH2>,
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<2 DMIC0 0x1 0 SWRM_TX1_CH4>,
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<2 DMIC1 0x2 0 SWRM_TX2_CH1>,
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<2 MBHC 0x4 0 SWRM_TX2_CH2>,
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<3 DMIC2 0x1 0 SWRM_TX2_CH3>,
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<3 DMIC3 0x2 0 SWRM_TX2_CH4>,
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<3 DMIC4 0x4 0 SWRM_TX3_CH1>,
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<3 DMIC5 0x8 0 SWRM_TX3_CH2>;
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qcom,wcd-rst-gpio-node = <&wcd937x_rst_gpio>;
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qcom,rx-slave = <&wcd937x_rx_slave>;
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qcom,tx-slave = <&wcd937x_tx_slave>;
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cdc-vdd-rxtx-supply = <&L11A>;
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qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
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qcom,cdc-vdd-rxtx-current = <30000>;
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cdc-vddpx-supply = <&L11A>;
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qcom,cdc-vddpx-voltage = <1800000 1800000>;
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qcom,cdc-vddpx-current = <30000>;
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cdc-vdd-buck-supply = <&L14A>;
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qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
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qcom,cdc-vdd-buck-current = <650000>;
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cdc-vdd-mic-bias-supply = <&BOB>;
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qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
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qcom,cdc-vdd-mic-bias-current = <45000>;
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qcom,cdc-micbias1-mv = <2800>;
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qcom,cdc-micbias2-mv = <2800>;
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qcom,cdc-micbias3-mv = <2800>;
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qcom,cdc-static-supplies = "cdc-vdd-rxtx",
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"cdc-vddpx",
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"cdc-vdd-mic-bias";
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qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
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};
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};
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&holi_snd {
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qcom,model = "holi-9370_aw882xx-snd-card";
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qcom,msm-mi2s-master = <1>, <1>, <1>, <1>;
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qcom,wcn-btfm = <1>;
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qcom,tdm-max-slots = <4>;
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qcom,sec-mi2s-gpios = <&cdc_sec_mi2s_gpios>;
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qcom,audio-routing =
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"AMIC1", "Analog Mic1",
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"Analog Mic1", "MIC BIAS1",
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"AMIC2", "Analog Mic2",
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"Analog Mic2", "MIC BIAS2",
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"AMIC3", "Analog Mic3",
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"Analog Mic3", "MIC BIAS3",
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"Analog Mic4", "MIC BIAS3",
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"TX DMIC0", "Digital Mic0",
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"TX DMIC0", "MIC BIAS1",
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"TX DMIC1", "Digital Mic1",
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"TX DMIC1", "MIC BIAS1",
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"TX DMIC2", "Digital Mic2",
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"TX DMIC2", "MIC BIAS3",
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"TX DMIC3", "Digital Mic3",
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"TX DMIC3", "MIC BIAS3",
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"IN1_HPHL", "HPHL_OUT",
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"IN2_HPHR", "HPHR_OUT",
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"IN3_AUX", "AUX_OUT",
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"RX_TX DEC0_INP", "TX DEC0 MUX",
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"RX_TX DEC1_INP", "TX DEC1 MUX",
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"RX_TX DEC2_INP", "TX DEC2 MUX",
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"RX_TX DEC3_INP", "TX DEC3 MUX",
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"TX SWR_INPUT", "WCD_TX_OUTPUT",
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"VA SWR_INPUT", "VA_SWR_CLK",
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"VA SWR_INPUT", "WCD_TX_OUTPUT",
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"VA_AIF1 CAP", "VA_SWR_CLK",
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"VA_AIF2 CAP", "VA_SWR_CLK",
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"VA_AIF3 CAP", "VA_SWR_CLK",
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"VA DMIC0", "Digital Mic0",
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"VA DMIC1", "Digital Mic1",
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"VA DMIC2", "Digital Mic2",
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"VA DMIC3", "Digital Mic3",
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"VA DMIC4", "Digital Mic4",
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"VA DMIC5", "Digital Mic5",
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"VA DMIC0", "VA MIC BIAS1",
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"VA DMIC1", "VA MIC BIAS1",
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"VA DMIC2", "VA MIC BIAS3",
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"VA DMIC3", "VA MIC BIAS3";
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qcom,msm-mbhc-hphl-swh = <1>;
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qcom,msm-mbhc-gnd-swh = <1>;
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asoc-codec = <&stub_codec>, <&bolero>,
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<&wcd937x_codec>,<&aw882xxacf>;
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asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
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"wcd937x_codec", "aw882xx_codec";
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qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>,
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<&bolero>;
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qcom,msm-mbhc-hs-mic-max-threshold-mv = <2700>;
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qcom,msm-mbhc-hs-mic-min-threshold-mv = <116>;
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};
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&qupv3_se10_i2c {
|
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status = "ok"
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aw882xxacf: aw882xxacf_smartpa@34 {
|
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compatible = "awinic,aw882xxacf_smartpa";
|
||||
reg = <0x34>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&aw882xx_irq_default>;
|
||||
irq-gpio = <&tlmm 59 0x2008>;
|
||||
dc-flag = <0>;
|
||||
sound-channel = <0>;
|
||||
aw-tx-topo-id = <0x1000ff00>;
|
||||
aw-rx-topo-id = <0x1000ff01>;
|
||||
aw-rx-port-id = <0x1002>;
|
||||
aw-tx-port-id = <0x1003>;
|
||||
aw-re-min = <4000>;
|
||||
aw-re-max = <30000>;
|
||||
aw-cali-mode = "aw_attr";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&va_cdc_dma_0_tx {
|
||||
qcom,msm-dai-is-island-supported = <1>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
wcd937x_rst_gpio: msm_cdc_pinctrl@32 {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&wcd937x_reset_active>;
|
||||
pinctrl-1 = <&wcd937x_reset_sleep>;
|
||||
};
|
||||
|
||||
clock_audio_rx_1: rx_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
|
||||
qcom,codec-lpass-ext-clk-freq = <22579200>;
|
||||
qcom,codec-lpass-clk-id = <0x30E>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_rx_2: rx_npl_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_5>;
|
||||
qcom,codec-lpass-ext-clk-freq = <22579200>;
|
||||
qcom,codec-lpass-clk-id = <0x30F>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_tx_1: tx_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x30C>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_tx_2: tx_npl_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_7>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x30D>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_va_1: va_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x30B>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_va_2: va_npl_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_8>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x310>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&adsp_loader {
|
||||
nvmem-cells = <&adsp_variant>;
|
||||
nvmem-cell-names = "adsp_variant";
|
||||
adsp-fw-names = "adsp2";
|
||||
adsp-fw-bit-values = <0x1>;
|
||||
};
|
||||
51
qcom/penang-sensors.dtsi
Executable file
51
qcom/penang-sensors.dtsi
Executable file
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
&tlmm {
|
||||
pen_int_default: pen_int_default {
|
||||
mux {
|
||||
pins = "gpio84";
|
||||
function = "gpio";
|
||||
};
|
||||
config {
|
||||
pins = "gpio84";
|
||||
num-grp-pins = <1>;
|
||||
drive-strength = <2>;
|
||||
bias-no-pull;
|
||||
};
|
||||
};
|
||||
|
||||
pen_int_sleep: pen_int_sleep {
|
||||
mux {
|
||||
pins = "gpio84";
|
||||
function = "gpio";
|
||||
};
|
||||
config {
|
||||
pins = "gpio84";
|
||||
num-grp-pins = <1>;
|
||||
drive-strength = <2>;
|
||||
bias-no-pull;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
pen_detect{
|
||||
compatible = "rohm,bu520xx_pen_detect";
|
||||
pinctrl-names = "default","sleep";
|
||||
pinctrl-0 = <&pen_int_default>;
|
||||
pinctrl-1 = <&pen_int_sleep>;
|
||||
rohm,nirq-gpio=<&tlmm 84 0x02>;
|
||||
};
|
||||
};
|
||||
|
||||
Loading…
Reference in a new issue